Index
© National Instruments Corporation Index-13 Lab-NB User Manual
and timebase source for
counter A0, 4-40, 4-43
A/D FIFO Register
clearing, 4-39, 4-41, 4-44,
4-47, 4-50
description, 4-10 to 4-11
output binary modes, 4-38
reading results of A/D
conversion, 4-37
servicing DAQ operation, 4-42,
4-45, 4-48, 4-50
storing results of A/D
conversion, 4-37
overview, 4-5
Status Register, 4-9
Analog Output Register group, 4-13
to 4-15
DAC Configuration Register
description, 4-14
setting up for interrupt
programming, 4-54
DAC0 and DAC1 Data Registers
description, 4-15
interrupt programming of analog
output circuitry, 4-54 to 4-55
loading DAC0 and DAC1
signals, 4-52
overview, 4-13
Configuration EPROM, 4-35
Interrupt Control Register group, 4-30
to 4-34
Interrupt Control Register, 4-31
to 4-32
Interrupt Status Register, 4-33
overview, 4-30
Timer Interrupt Clear Register, 4-34
map for Lab-NB (table), 4-3
programming considerations, 4-35
sizes of registers, 4-4
slot address space, 4-1
24-bit mode (table), 4-2
32-bit mode (table), 4-2
S
sample-interval counter, programming
controlled acquisition mode, 4-41
freerun acquisition mode, 4-44
sample-interval timer, 3-5
SCANEN bit
DAQ operations on single input
channel, 4-40
description, 4-7
multiple A/D conversions with channel
scanning, 4-51 to 4-52
selecting posttrigger mode, 4-47
selecting pretrigger mode, 4-49
scanned (multichannel) data acquisition, 3-5
signal connections, 2-5 to 2-24
analog input signal connections, 2-7
to 2-8
analog output signal connections, 2-9
descriptions (table), 2-7
digital I/O signal connections, 2-10
to 2-16
digital input specifications, 2-10
digital output specifications, 2-10
mode 1 input timing, 2-14
mode 1 output timing, 2-15
mode 2 bidirectional timing, 2-16
Port C pin connections, 2-11 to 2-12
timing specifications, 2-12 to 2-13
typical digital I/O applications
(figure), 2-11
I/O connector pin descriptions, 2-5
to 2-6
timing connections, 2-17 to 2-24
DAQ timing connections, 2-17
to 2-21
event-counting application with
external switch gating
(figure), 2-22
EXTCONV* signal timing
(figure), 2-17
frequency measurement application
(figure), 2-23
general-purpose timing signal
connections, 2-21 to 2-24
requirements for GATE and CLK
and OUT signals (figure), 2-24
NuBus interrupt generation with
EXTUPDATE* signal
(figure), 2-20
posttrigger DAQ timing (figure)
EXTCONV* high, 2-18