Register-Level Programming Chapter 4
Lab-NB User Manual 4-46 © National Instruments Corporation
Using the EXTTRIG Signal to Terminate a Multiple A/D Conversion DAQ Operation
(Pretrigger Mode)
If the PRETRIG bit is set in the ADC Command Register, EXTTRIG functions as a stop trigger
for a multiple A/D conversion DAQ operation. In this mode, referred to as pretriggering, the
sample counter is gated off until a low-to-high edge is sensed on EXTTRIG. Pretriggering is
performed in a manner similar to external triggering. With pretriggering, counter A0 (the
sample-interval counter) starts as soon as the last byte is loaded. However, counter A1, the
sample counter, does not start counting until the first rising edge on EXTTRIG. In this way, data
is collected before the actual trigger rising edge. After the rising edge occurs, the number of
points specified in counter A1 are collected and the acquisition stops. You must allocate
sufficient array space for all of the data, and specify both the number of points and the
indeterminate number of points that may be collected before the pretrigger signal arrives.
Alternatively, a circular buffer can be set up by the acquisition software so that data is repeatedly
loaded into the same section of memory. Although this method does not require an
indeterminate amount of memory, you can examine only samples acquired during a limited time
period before and after the trigger occurs. Pretriggering is set up by setting PRETRIG in the
ADC Configuration Register. PRETRIG supersedes EXTTRIGEN; if both bits are set, then
pretriggering is enabled.
Using the EXTCONV* Signal to Initiate A/D Conversions
As mentioned earlier, A/D conversions can be initiated by a falling edge on either OUTA0 or
EXTCONV*. Setting the GATA0 bit low disables conversions from both OUTA0 and
EXTCONV*. Setting the GATA0 bit high enables conversions from both OUTA0 and
EXTCONV*. The GATA0 bit is set low whenever OUTA1 is high. If OUTA1 is low, GATA0
can be set high at any time by either setting the PRETRIG bit or initiating a rising edge on
EXTRIG if the EXTRIGEN bit in the ADC Command Register is set.
Programming Multiple A/D Conversions Using External Timing
A DAQ operation using the external timing signals EXTCONV* or EXTTRIG can be in either
controlled acquisition mode or freerun acquisition mode. In controlled acquisition mode, counter
A1 shuts off A/D conversions after the programmed count expires. In freerun acquisition mode,
A/D conversions are disabled under software control.
Programming in Controlled Acquisition Mode
Posttrigger Mode
The following programming steps are required for a DAQ operation in controlled acquisition
mode using EXTCONV*. In the following programming sequence, EXTTRIG is used as a
posttrigger signal; that is, data acquisition is not started until a rising edge is detected on the
EXTTRIG input.
1. Disable EXTCONV* and EXTTRIG input.
2. Select analog input channel and gain and select posttrigger mode.
3. Program counter A0.