Theory of Operation Chapter 3

Lab-NB User Manual 3-10 © National Instruments Corporation

All three ports on the 82C55A are TTL-compatible. When enabled, the digital output ports are

capable of sinking 2.5 mA of current and sourcing 2.5 mA of current on each digital I/O line.

When the ports are not enabled, the digital I/O lines act as high-impedance inputs.

Timing I/O Circuitry

The Lab-NB uses two 8253 Counter/Timer integrated circuits for DAQ timing and for general-

purpose timing I/O functions. One of these is used internally for DAQ timing, and the other is

available for general use. Figure 3-6 shows a block diagram of both groups of timing I/O

circuitry (counter groups A and B).

MUX
1-MHz Source OUTB0
TBSEL
CTR RD
CTR WR
Data
8
OUTA0
Sample
Interval
Counter
CLKA0
GATEA0
CLKA1
Sample
Counter
GATEB2
CLKB2
OUTB2
GATEB1
CLKB1
OUTB1
OUTB0
GATEB0
CLKB0
8253
Counter/Timer
Group B
2-MHz
Source
A/D Conversion Logic
I/O Connector
GATEA1
OUTA1
CLKA2
GATEA2
DAC
Timing
OUTA2
8253
Counter/Timer
Group A
D/A Conversion Timing
+5 V
EXTUPDATE*
EXTTRIG
EXTCONV*
NuBus

Figure 3-6. Timing I/O Circuitry Block Diagram