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Low-Cost Multifunction I/O Board for ISA Lab-PC+ manual
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211 pages, 3.02 Mb
© Copyright 1992, 1996 National Instruments Corporation.
All Rights Reserved.
Lab-PC+
User Manual
Low-Cost Multifunction I/O Board for ISA
June 1996 Edition
Part Number 320502B-01
Contents
Main
Page
Warranty
Copyright
Trademarks
Page
Contents
About This Manual
Chapter 1 Introduction
Chapter 2 Configuration and Installation
Chapter 3 Signal Connections
Chapter 4 Theory of Operation
Page
Figures
Tables
About This Manual
Organization of the Lab-PC+ User Manual
Conventions Used in This Manual
National Instruments Documentation
Customer Communication
Chapter 1 Introduction
About the Lab-PC+
What You Need to Get Started
Software Programming Choices
LabVIEW and LabWindows/CVI Application Software
NI-DAQ Driver Software
Register-Level Programming
Optional Equipment
Unpacking
Chapter 2 Configuration and Installation
Board Configuration
PC Bus Interface
Configuration and Installation Chapter 2
Figure 2-1. Parts Locator Diagram
Lab-PC+ User Manual 2-2 National Instruments Corporation
Base I/O Address Selection
Page
Page
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Analog I/O Configuration
Analog Output Configuration
Analog Input Configuration
Page
Page
Analog Input Polarity Configuration
Page
Hardware Installation
Chapter 3 Signal Connections
I/O Connector Pin Description
Signal Connections Chapter 3
Lab-PC+ User Manual 3-2 National Instruments Corporation
Figure 3-1. Lab-PC+ I/O Connector Pin Assignments
Signal Connection Descriptions
Page
Analog Input Signal Connections
Types of Signal Sources
Floating Signal Sources
Ground-Referenced Signal Sources
Input Configurations
Differential Connection Considerations (DIFF Configuration)
Differential Connections for Grounded Signal Sources
Differential Connections for Floating Signal Sources
Page
Single-Ended Connection Considerations
Single-Ended Connections for Floating Signal Sources (RSE Configuration)
Single-Ended Connections for Grounded Signal Sources (NRSE Configuration)
Common-Mode Signal Rejection Considerations
Analog Output Signal Connections
Digital I/O Signal Connections
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Timing Connections
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Cabling
Chapter 4 Theory of Operation
Figure 4-1. Lab-PC+ Block Diagram
Functional Overview
The block diagram in Figure 4-1 shows a functional overview of the Lab-PC+ board.
PC I/O Channel Interface Circuitry
Page
Theory of Operation Chapter 4
Lab-PC+ User Manual 4-4 National Instruments Corporation
Analog Input and Data Acquisition Circuitry
Figure 4-3. Analog Input and Data Acquisition Circuitry Block Diagram
Analog Input Circuitry
Data Acquisition Timing Circuitry
Page
Page
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Analog Output Circuitry
Digital I/O Circuitry
Timing I/O Circuitry
Theory of Operation Chapter 4
Figure 4-6. Timing I/O Circuitry Block Diagram
PC I/O Channel
Lab-PC+ User Manual 4-12 National Instruments Corporation
I/O Connector
Page
Page
Chapter 5 Calibration
Calibration Equipment Requirements
Calibration Trimpots
Analog Input Calibration
Board Configuration
Bipolar Input Calibration Procedure
Unipolar Input Calibration Procedure
Analog Output Calibration
Board Configuration
Bipolar Output Calibration Procedure
Page
Unipolar Output Calibration Procedure
Appendix A Specifications
Analog Input
Page
Explanation of Analog Input Specifications
Analog Output
Explanation of Analog Output Specifications
Digital I/O
Timing I/O
Triggers
Bus Interface Power Requirements (from PC)
Physical
Environment
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Register Sizes
Register Description
Register Description Format
Configuration and Status Register Group
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Analog Input Register Group
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8253 Counter/Timer Register Groups A and B
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Interval Counter Register Group
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Appendix E Register-Level Programming
Register Programming Considerations
Initializing the Lab-PC+ Board
Programming the Analog Input Circuitry
Analog Input Circuitry Programming Sequence
A/D FIFO Output Binary Modes
Clearing the Analog Input Circuitry
Programming Multiple A/D Conversions on a Single Input Channel
Programming in Controlled Acquisition Mode
Page
Programming in Freerun Acquisition Mode
Page
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External Timing Considerations for Multiple A/D Conversions
Using the EXTCONV* Signal to Initiate A/D Conversions
Programming Multiple A/D Conversions Using External Timing
Programming in Controlled Acquisition Mode
Page
Page
Page
Programming in Freerun Acquisition Mode
Programming Multiple A/D Conversions with Channel Scanning
Programming Multiple A/D Conversions with Interval Scanning
Programming Multiple A/D Conversions in Single-Channel Interval Acquisition Mode
A/D Interrupt Programming
Programming DMA Operation
Programming the Analog Output Circuitry
Page
Interrupt Programming for the Analog Output Circuitry
Programming the Digital I/O Circuitry
Register Descriptions and Programming Examples
Figure E-1. Control-Word Format with Control-Word Flag Set to 1
Modes of Operation for the 8255A
Mode 0
Page
Mode 1
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Mode 2
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Interrupt Programming for the Digital I/O Circuitry
Appendix F Customer Communication
Technical Support Form
Lab-PC+ Hardware and Software Configuration Form
National Instruments Products
Other Products
Documentation Comment Form
Glossary
Page
Index
Numbers
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