Index
© National Instruments Corporation Index-7 Lab-PC+ User Manual
Mode 1 output, E-29 to E-31
control words, E-29
Port C pin assignments, E-30
Port C status-word bit definitions, E-30
programming example, E-30
Mode 2 operation, E-31 to E-34
control words, E-31 to E-32
Port C pin assignments, E-33
Port C status-word bit definitions, E-32
programming example, E-33
single bit set/reset control words, E-33
single bit set/reset feature, E-34
Digital I/O Register Group. See 8255A Digital
I/O Register Group.
digital I/O signal connections, 3-13 to 3-20
illustration, 3-15
Mode 1 input timing, 3-18
Mode 1 output timing, 3-19
Mode 2 bidirectional timing, 3-20
Port C pin connections, 3-15 to 3-16
specifications and ratings, 3-14
timing specifications, 3-16 to 3-17
digital I/O specifications, A-5
DIOINTEN bit
description, D-12
digital I/O circuitry programming, E-34
DMA channel selection, 2-6 to 2-7
factory settings (table), 2-3
jumper settings
disabling DMA transfers (figure), 2-7
factory settings (figure), 2-6
jumper settings (figure), 2-6
signal lines (table), 2-6
DMA control circuitry
programming, E-20
theory of operation, 4-4
DMAEN bit
description, D-12
DMA request generation, E-20
DMATC bit
description, D-7
DMA request generation, E-20
DMATC Interrupt Clear Register
description, D-20
DMA request generation, E-20
documentation
conventions used in manual, xii
National Instruments documentation, xiii
organization of manual, xi-xii
E
ECKDRV bit, D-14
ECLKRCV bit, D-13
environment specifications, A-6
EOIRCV bit
description, D-14
multiple A/D conversions
interval scanning, E-17 to E-18
single-channel interval acquisition
mode, E-19
equipment, optional, 1-4
ERRINTEN bit
A/D interrupt programming, E-20
description, D-11
event counting, 3-25
application with external switch gating
(figure), 3-25
EXTCONV* signal
data acquisition timing, 3-21 to 3-22
description (table), 3-3
external timing for multiple A/D
conversions, E-12
controlled acquisition mode
posttrigger mode, E-12 to E-13
pretrigger mode, E-14 to E-15
freerun acquisition mode
posttrigger mode, E-16
initiation of A/D conversions, E-12
overview, E-11
posttrigger data acquisition timing
(figure), 3-22
external timing for multiple A/D conversions.
See multiple A/D
conversions, programming.
EXTGATA0 bit, D-7
EXTTRIG signal
data acquisition timing, 3-21 to 3-23
description (table), 3-3
external timing for multiple A/D
conversions, E-12
controlled acquisition mode
posttrigger mode, E-12 to E-13
pretrigger mode, E-14 to E-15
initiation (posttrigger mode), E-11
overview, E-11
termination (pretrigger mode), E-11
posttrigger data acquisition timing
(figure), 3-22