National Instruments NI 6115, NI 6120 Phase-Locked Loop Circuit

Chapter 3 Hardware Overview

© National Instruments Corporation 3-9 NI 6115/6120 User Manual

Figure 3-9. Effects of Hardware and Software Filtering on Antialiasing

Phase-Locked Loop Circuit

♦NIPXI-6115/6120

A phase-locked loop (PLL) circuit accomplishes the synchronization of

multiple NIPXI-6115/6120 devices or other PXI devices which support

PLL synchronization by allowing these devices to all lock to the same

reference clock present on the PXI backplane. This circuit allows you to

trigger input or output operations on different devices and ensures that

samples occur at the same time.

The PLL circuitry consists of a voltage-controlled crystal oscillator

(VCXO) with a tuning range of ±50ppm. The VCXO generates the

60MHz master clock used onboard the NI PXI-6115/6120.

The PLL locks to the 10 MHz oscillator line on the PXI backplane bus.

Aphase comparator running at 1 MHz compares the PXI Bus and VCXO

clock. The loop filter then processes the error signal and outputs a control

voltage for the VCXO. Figure3-10 illustrates the block diagram for the

NIPXI-6115/6120.

Note This feature is not available on the NIPCI-6115/6120.

The PLL circuit is automatically enabled when the NI 6115/6120 is

powered up. No configuration steps are required in order to utilize PLL

synchronization.

f

cutoff

f

Nyquist

(2 f

cutoff

)

4 f

cutoff

Response of Analog Hardware Filters

Response of Software Filters

Contents

Main Page Important Information Warranty Copyright Trademarks Patents Compliance FCC/Canada Radio Frequency Interference Compliance Determining FCC Class FCC/DOC Warnings Class A Compliance to EU Directives Contents Chapter 4 Connecting Signals Page About This Manual Conventions National Instruments Documentation Related Documentation Introduction About the NI 6115/6120 Using PXI with CompactPCI What You Need to Get Started Software Programming Choices NI-DAQ National Instruments ADE Software Optional Equipment Custom Cabling Unpacking Safety Information Page Page Installing and Configuring the NI 6115/6120 Installing the Software Installing the Hardware Page Configuring the Device National Instruments Corporation 3-1 NI 6115/6120 User Manual Hardware Overview DAQ - STC RTSI Bus Figure 3-1. NI 6115 Block Diagram Analog Input The following sections describe in detail each AI category. Input Mode Note The inputs are differential only in the sense that the ground loops are broken. I/O Connector Input Polarity and Input Range Considerations for Selecting Input Ranges Input Coupling Analog Output Analog Trigger Figure 3-3. Analog Trigger Block Diagram for the NI 6115/6120 Figure 3-4. Below-Low-Level Analog Triggering Mode Page Antialiasing Filters Phase-Locked Loop Circuit Correlated Digital I/O Timing Signal Routing Page Programmable Function Inputs Device and RTSI Clocks RTSI Triggers Page Figure 3-13. PXI RTSI Bus Signal Connections Connecting Signals I/O Connector Figure 4-1. I/O Connector Pin Assignment for the NI 6115/6120 I/O Connector Signal Descriptions Table 4-2. Signal Descriptions for I/O Connector Pins Table 4-2. Signal Descriptions for I/O Connector Pins (Continued) Table 4-3. Analog I/O Signal Summary for the NI 6115 Table 4-2. Signal Descriptions for I/O Connector Pins (Continued) Table 4-4. Analog I/O Summary for the NI 6120 Table 4-5. Digital I/O Signal Summary Types of Signal Sources Floating Signal Sources Table 4-5. Digital I/O Signal Summary (Continued) Ground-Referenced Signal Sources Connecting Analog Input Signals Connections for Ground-Referenced Signal Sources * Figure 4-2. Pseudodifferential Input Connections on the NI 6115 forGro und-Referenced Signals Figure 4-3. Pseudodifferential Input Connections on the NI 6120 forGro und-Referenced Signals Connections for Nonreferenced or Floating Signal Sources * Figure 4-4. Differential Input Connections on the NI 6115 for Nonreferenced Signals Common-Mode Signal Rejection Considerations Working Voltage Range Connecting Analog Output Signals Connecting Digital I/O Signals Correlating DIO Signal Connections Page Power Connections Connecting Timing Signals Page Programmable Function Input Connections DAQ Timing Connections TRIG1 Signal TRIG2 Signal Page STARTSCAN Signal Page CONVERT* Signal AIGATE Signal SISOURCE Signal SCANCLK Signal EXTSTROBE* Signal Waveform Generation Timing Connections WFTRIG Signal UPDATE* Signal UISOURCE Signal General-Purpose Timing Signal Connections GPCTR0_SOURCE Signal GPCTR0_GATE Signal GPCTR0_OUT Signal GPCTR0_UP_DOWN Signal GPCTR1_SOURCE Signal GPCTR1_GATE Signal GPCTR1_OUT Signal Figure4-34 shows the timing requirements for GPCTR1_OUT. Figure 4-35. GPCTR1_OUT Signal Timing Figure 4-36. GPCTR Timing Summary GPCTR1_UP_DOWN Signal FREQ_OUT Signal Field Wiring Considerations Calibration Loading Stored Calibration Constants Self-Calibration External Calibration Page A Specifications Analog Input Input Characteristics DC Transfer Characteristics Table A-1. NI 6115 Analog Input DC Accuracy Information Table A-2. NI 6120 Analog Input DC Accuracy Information Dynamic Characteristics Table A-4. NI6120 Analog Input Dynamic Charac teristics Figure A-1. NI 6115 Total Harmonic Distortion Plus Noise (THD+N) Figure A-2. NI 6120 Total Harmonic Distortion Plus Noise (THD+N) Figure A-3. NI6115 High-Voltage THD + N Figure A-4. NI 6120 High-Voltage THD+ N Figure A-5. NI 6115 THD + N with Filters Stability Analog Output Output Characteristics DC Transfer Characteristics Voltage Output Dynamic Characteristics Stability Digital I/O Timing I/O Triggers Analog Trigger Page Safety Maximum Working Voltage Electromagnetic Compatibility B Common Questions General Information Installing and Configuring the Device Analog Input and Output Page Timing and Digital I/O Page C Technical Support and Professional Services Glossary Numbers/Symbols A B C D E F G H I K L M N O P R S T U V W Index Numerics A B C D E F G H I K L M N O P Q R S Page T U V W