National Instruments PC-LPM-16/PnP - page 62

Appendix C Using Your PC-LPM-16 (Non-PnP) Board

PC-LPM-16/PnP User Manual C-2



National Instruments Corporation

Data FIFO Size 16 words 512 words 256 words

Dummy reads to A/D

and FIFO high-byte

and low-byte registers

after clearing data

FIFO

Required Not required, but

allowed Not required, but

allowed

ADC FIFO Data

Reading Order Low byte before

high byte preferred Low byte must be

read before high

byte

Low byte must be

read before high

byte

Overflow Error Bit

Location Status Register 1,

bit 1 Status Register 1,

bit 1 Status Register 2,

bit 1

Overrun Error Bit

Location Not implemented Not implemented Status Register 2,

bit 0

Data Error Bit

Location Not implemented Not implemented Status Register 1,

bit 1

5 and 12 V Supply

Fuses Nonresettable Self-resetting Self-resetting

-12 V Supply Power

Requirements 0 mA 15 mA typ 15 mA typ

Performance Specification Changes

INL

±

1 LSB max

±

0.5 LSB max

±

0.5 LSB max

Gain Error,

±

2.8 V or

to 10 V Range

±

3 LSB typ,

±

7 LSB max

±

2 LSB typ,

±

4 LSB max

±

2 LSB typ,

±

4 LSB max

Calibration Time 700

µ

s typ 10 ms typ 10 ms typ

Overvoltage

Protection or Analog

Input Powered Off

±

45 V

±

35 V

±

35 V

Table C-1.

Comparison of Characteristics (Continued)

Functional Changes Legacy PC-LPM-16 Revised PC-LPM-16 PC-LPM-16PnP

Contents

Main Page Important Information WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS Trademarks Copyright Page Page Glossary Index Figures Tables About This Manual Organization of This Manual Conventions Used in This Manual National Instruments Documentation Related Documentation Customer Communication Introduction About the PC-LPM-16/PnP What You Need to Get Started LabVIEW and LabWindows/CVI Application Software Software Programming Choices NI-DAQ Driver Software Register-Level Programming Optional Equipment Custom Cables Unpacking Installation and Configuration Hardware Installation Software Installation Plug and Play Board Configuration Base I/O Address and Interrupt Selection Non-Plug and Play Theory of Operation Functional Overview Chapter 3 Theory of Operation Figure 3-1. PC-LPM-16PnP Block Diagram PC I/O Channel Interface Circuitry Analog Input and Data Acquisition Circuitry Analog Input Circuitry Data Acquisition Timing Circuitry Single-Channel Data Acquisition Data Acquisition Rates Multichannel Scanning Data Acquisition Chapter 3 Theory of Operation PC-LPM-16/PnP User Manual 3-8 Digital I/O Circuitry Digital I/O Circuitry Block Diagram Figure 3-4. Timing I/O Circuitry Page Signal Connections I/O Connector Chapter 4 Signal Connections Figure 4-1. PC-LPM-16PnP I/O Connector Pin Assignments Signal Connection Descriptions Page Analog Input Signal Connections Connections for Signal Sources Digital I/O Signal Connections Power Connections Power Rating Data Acquisition Timing Connections Timing Connections General-Purpose Timing Signal Connections and General-Purpose Counter Timing Signals Page Page Page Specifications A Transfer Characteristics PC-LPM-16PnP Board Amplifier Characteristics Digital I/O Stability Dynamic Characteristics Timing I/O Bus Interface Explanation of Analog Input Specifications Environment Physical Page Page B MSM82C53 Data Sheet Page Page Page Page Page Page Page Page Page Page Page Using Your PC-LPM-16 (Non-PnP) Board C the PC-LPM-16 Differences between the PC-LPM-16PnP and Page Page Configuration and Installation of the Board Configuration PC-LPM-16 (non-PnP) Page Base I/O Address Selection Page Page Interrupt Selection Analog Input Jumper Settings 5 V) Bipolar Input Selection 1 ( Bipolar Input Selection 2 ( Unipolar Input Selection 1 (0 to 10 V) Select the bipolar ( 2.5 V) 2.5 V) input configuration by setting jumpers W1 and W2 as shown in Figure C-6. Unipolar Input Selection 2 (0 to 5 V) Installation Register-Level Programming D Register Map Base Address Register Size Register Descriptions Register Description Format Configuration and Status Register Group Page Page Page Command Register 2 Command Register 2 Command Register 3 Status Register 1 Status Register 1 Page Status Register 2 Analog Input Register Group A/D FIFO Low-Byte Register and A/D FIFO High-Byte Register A/D FIFO Low-Byte Register and A/D FIFO High-Byte Register A/D Clear Register Counter/Timer (MSM82C53) Register Group Counter 0 Data Register Counter 1 Data Register Counter 2 Data Register Page Page Page Timer Interrupt Clear Register Digital I/O Register Group Digital Output Register Digital Input Register Programming Considerations Register Programming Considerations Initializing the PC-LPM-16/PnP Programming the A/D Calibration Programming the Analog Input Circuitry Analog Input Circuitry Programming Sequence A/D FIFO Output Binary Modes Clearing the Analog Input Circuitry Programming Multiple A/D Conversions on a Single Input Channel Using Counter 0 Page Page Programming Multiple A/D Conversions Using External Timing Programming Multiple A/D Conversions with Channel Scanning A/D Interrupt Programming Programming the Digital I/O Circuitry Programming the MSM82C53 Counter/Timer Customer Communication FTP Support Electronic Services E Bulletin Board Support Telephone and Fax Support Telephone Fax Fax-on-Demand Support E-Mail Support (currently U.S. only) Technical Support Form PC-LPM-16/PnP Hardware and Software Configuration Form Other Products National Instruments Products Documentation Comment Form Glossary Symbols A C B Page Page T V A Numbers Index B C D E I H F G J P N M O R S T U