3.3.6Interrupt Polarity Control Register

(Read/Write): wBase+0x2A

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

0

0

0

INV3

INV2

INV1

INV0

Note. Refer to Sec. 3.1 for more information about wBase.

INV0=1Æ select the non-inverted signal from PC0

INV0=0Æ select the inverted signal from PC0

outportb(wBase+0x2a,0x0f);

/* select the non-inverted input PC0/1/2/3

*/

outportb(wBase+0x2a,0x00);

/* select the inverted input of PC0/1/2/3

*/

outportb(wBase+0x2a,0x0e); /* select the inverted input of PC0

*/

 

/* select the non-inverted input PC1/2/3

*/

outportb(wBase+0x2a,0x0c); /* select the inverted input of PC0/1

*/

 

/* select the non-inverted input PC2/3

*/

Refer to Sec. 2.4 for more information.

Refer to DEMO5.C for more information.

3.3.7I/O Selection Control Register

(Write): wBase+0xcc

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

0

0

0

0

Port2

Port1

Port0

Note. Refer to Sec. 3.1 for more information about wBase.

Port? = 1Æ this port is used as a D/O port

Port? = 0Æ this port is used as a D/I port

outportb(wBase+0xcc,0x00);

/* configure Port0/1/2 as D/I port

*/

outportb(wBase+0xcc,0x04);

/* configure Port0/1 as D/I port

*/

 

/* configure Port2 as D/O port

*/

OME-PIO-D56/PIO-D24 User Manual (Ver.2.1, Oct/2003, PPH-005-21)

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Omega Vehicle Security OME-PIO-D56 manual Interrupt Polarity Control Register, 7 I/O Selection Control Register