if (wIrq<8)
{
irqmask=inportb(A1_8259+1);
outportb(A1_8259+1,irqmask & 0xff ^ (1<<wIrq)); setvect(wIrq+8,irq_service);
}
else
{
irqmask=inportb(A1_8259+1);
outportb(A1_8259+1,irqmask & 0xfb);/* IRQ2 */ irqmask=inportb(A2_8259+1);
outportb(A2_8259+1,irqmask & 0xff ^
}
invert=0x05; |
| /* PC0 | = | |||
outportb(wBase+0x2a,invert); |
| |||||
|
|
| /* PC1 | = | inverte input */ | |
|
|
| /* PC2 | = | ||
|
|
| /* PC3 | = | inverte input */ | |
now_int_state=0x0a; |
| /* PC0 | = Low |
| */ | |
|
|
| /* PC1 | = High |
| */ |
|
|
| /* PC2 | = Low |
| */ |
|
|
| /* PC3 | = High |
| */ |
CNT_L1=CNT_L2=CNT_L3=CNT_L4=0; |
| /* Low_pulse counter | */ | |||
CNT_H1=CNT_H2=CNT_H3=CNT_H4=0; |
| /* High_pulse counter | */ | |||
int_num=0; |
| /* enable interrupt PC0,PC1 | */ | |||
outportb(wBase+5,0x0f); |
| |||||
enable(); |
| /* PC2,PC3 |
| */ | ||
} |
|
|
|
|
| */ |
/* |
|
|
|
| ||
/* NOTE:1.The | */ | |||||
/* | 2.The ISR must read the interrupt status again to the | */ | ||||
/* | active interrupt sources. |
|
|
| */ | |
/* | 3.The INT_CHAN_0&INT_CHAN_1 can be active at the same time*/ | |||||
/* |
|
|
|
| */ | |
void interrupt irq_service() |
|
|
|
|
| |
{ |
|
|
|
|
|
|
char c; |
|
|
|
|
|
|
int_num++; |
| /* read all interrupt state */ | ||||
new_int_state=inportb(wBase+7)&0x0f; | ||||||
int_c=new_int_state^now_int_state; | /* compare which interrupt | */ | ||||
if ((int_c&0x1)!=0) |
| /* signal be change | */ | |||
| /* INT_CHAN_0 is active | */ | ||||
{ |
|
|
|
|
| */ |
if ((new_int_state&0x1)!=0)/* now PC0 is change to high | ||||||
{ |
|
|
|
|
|
|
CNT_H1++; |
|
|
|
|
| |
} |
| /* now PC0 is change to low | */ | |||
else |
| |||||
{ |
|
|
|
|
|
|
CNT_L1++; |
|
|
|
|
| |
} |
| /* to generate a high pulse | */ | |||
invert=invert^1; | ||||||
} |
|
| /* INT_CHAN_1 is active | */ | ||
if ((int_c&0x2)!=0) |
| |||||
{ |
|
|
|
|
| */ |
if ((new_int_state&0x2)!=0)/* now PC1 is change to high | ||||||
{ |
|
|
|
|
|
|
CNT_H2++;
}
