Philips ISP1521 - page 18

Philips Semiconductors ISP1521

Hi-Speed USB hub controller

Product data Rev. 03 — 24 November 2004 18 of 53

9397 750 13702 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.

9.2.2 Architecture of conﬁgurable hub descriptors

The conﬁgurable hub descriptors can be masked in the internal ROM memory; see

Figure 7. These descriptors can also be supplied from an external EEPROM or a

microcontroller. The ISP1521 implements both the master and slave I2C-bus

controllers. The information from the external EEPROM or the microcontroller is

transferred into the internal RAM during the power-on reset. A signature word is used

to identify correct descriptors. If the signature matches, the content of the RAM is

chosen instead of the ROM.

When the external microcontroller mode is selected and while the external

microcontroller is writing to the internal RAM, any request to conﬁgurable descriptors

will be responded to with a Not AcKnowledge (NAK). There is no speciﬁed time-out

period for the NAK signal. This data is then passed to the host during the

enumeration process.

The three conﬁguration methods are selected by connecting pins SCL and SDAin the

manner given in Tabl e 11.

The I2C-bus cannot be shared between the EEPROM and the external microcontroller.

Fig 7. Conﬁgurable hub descriptors.

Table 11: Conﬁguration method

Conﬁguration method SCL SDA

Internal ROM ground ground

External EEPROM 2.2kΩ to 4.7 kΩ pull-up 2.2 kΩ to 4.7kΩ pull-up

External microcontroller driven LOW by the

microcontroller during reset 2.2 kΩ to 4.7 kΩ pull-up

MLD711

MICROCONTROLLER SERIAL EEPROM

MASTER/SLAVE

I

2

C-BUS INTERFACE

signature

match

RAM

(256 bytes)

DESCRIPTOR

GENERATOR

INTERFACE

ROM

(256 bytes)

MUX

HUB CORE

I

2

C-bus

Contents

Main ISP1521 Hi-Speed Universal Serial Bus hub controller Universal Serial Bus Specication Rev.2.0 Rev. 03 24 November 2004 Product data 1. General description 2. Features Universal Serial Bus Specication Rev.2.0 3. Applications 4. Abbreviations 5. Ordering information Product data Rev. 03 24 November 2004 4 of 53 6. Block diagram Fig 1. Block diagram. ISP1521 Philips Semiconductors ISP1521 Product data Rev. 03 24 November 2004 5 of 53 7. Pinning information Fig 2. Pin conguration. 7.2 Pin description 7.1 Pinning ISP1521BE Page ISP1521 Hub Demo Board Users Guide Page Page 8. Functional description 8.3 Phase-locked loop clock multiplier 8.4 I2C-bus controller 8.5 Overcurrent detection circuit 8.6 GoodLink 8.7 Power-on reset Fig 4. External clock with respect to power-on reset. Fig 3. Power-on reset timing. Stable external clock is to be available at A. 9. Conguration selections 9.1 Conguration through I/O pins Philips Semiconductors ISP1521 pull-up Fig 6. Typical voltage drop components in the self-powered mode using global overcurrent detection. PSWn_N pins have integrated weak pull-up resistors inside the chip. (1) Includes PCB traces, ferrite beads, and so on. Page 9.2 Device descriptors and string descriptors settings using I2C-bus The I C-bus specication Page 9.2.3 ROM or EEPROM map Page Philips Semiconductors ISP1521 Page Page 10. Hub controller description 11. Descriptors Page Page 12. Hub requests Tab le 23 shows the suppor ted standard USB requests. 12.1 Standard USB requests 12.2 Hub class requests Tab le 24 shows the hub class requests. 12.3 Detailed responses to hub requests Page Page 12.4 Various get descriptors bmRequestType 10000000B bmRequest GET_DESCRIPTOR = 6 13. Limiting values 14. Recommended operating conditions In accordance with the Absolute Maximum Rating System (IEC 60134). 15. Static characteristics Page Page 16. Dynamic characteristics C; test circuit Figure 21; unless otherwise specied. Page TPERIOD is the bit duration corresponding with the USB data rate. Fig 11. Source differential data-to-EOP transition skew and EOP width. TPERIOD is the bit duration corresponding with the USB data rate. tJR is the jitter reference point. Fig 13. Receiver SE0 width tolerance. Fig 12. Receiver differential data jitter. Fig 14. Hub differential data delay and SOP distortion. Fig 15. Hub EOP delay and EOP skew. and T within recommended operating range; V =5V; V =V ; V 17. Application information 17.1 Descriptor conguration selection ISP1521 Fig 18. Adjusting analog overcurrent detection limit (optional). . . 17.3 Self-powered hub congurations ISP1521 Fig 19. Self-powered hub; individual port power switching; individual overcurrent detection. Fig 20. Self-powered hub; ganged port power switching; global overcurrent detection. ISP1521 18. Test information DMn D Fig 22. Full-speed test circuit. Fig 21. High-speed transmitter and receiver test circuit. 19. Package outline LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm SOT315-1 Fig 23. LQFP80 package outline. 20. Soldering 20.1 Introduction to soldering surface mount packages Data Handbook IC26; Integrated Circuit Packages 20.2 Reow soldering 20.3 Wave soldering 21. Revision history Philips Semiconductors ISP1521 Contact information 22. Data sheet status 23. Denitions 24. Disclaimers 25. Licenses 26. Trademarks Contents