2001 Jul 23 12
Philips Semiconductors Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection TDA8586
Notes
1. Tolerances on the mute level is tight because of the usage of this pin for integration during load detection.
2. The output power is measured directly on the pins of the IC.
3. The noise output is measured in a bandwidth of 20 Hz to 20 kHz.
Gvvoltage gain Vi(rms) =15mV 313233dB
∆G
vchannel unbalance Vi(rms) =15mV −0.7 0 +0.7 dB
αcs channel separation Po= 2 W; fi= 1 kHz; RL=4Ω45 55 −dB
VOO DC output offset voltage VP= 14.4 V; on condition −0 100 mV
VP= 14.4 V; RL=4Ω;
mute condition −10 20 mV
Vn(o) noise output voltage on Rs=1kΩ; VP= 14.4 V; note 3 −100 150 µV
Vn(o)(mute) noise output voltage mute note 3 −020µV
V
o(mute) output voltage mute Vi(rms) =1V −3 500 µV
SVRR supply voltage ripple rejection: Rs=0Ω; fi= 1 kHz;
Vripple = 2 V (p-p)
on condition 45 55 −dB
mute condition 55 70 −dB
Ziinput impedance input referenced to ground 40 60 90 kΩ
Quad SE application (see Fig.8)
THD total harmonic distortion fi= 1 kHz; Po= 1 W; RL=4Ω− 0.05 0.15 %
45 Hz < fi< 10 kHz; Po=1W;
R
L=4Ω; filter: f < 30 kHz −0.5 −%
Pooutput power VP= 14.4 V; RL=4Ω; note 2
THD = 0.5% 4 4.5 −W
THD = 10% 5 6 −W
Gvvoltage gain Vi(rms) =15mV 252627dB
∆G
vchannel unbalance Vi(rms) =15mV −0.7 0 +0.7 dB
αcs channel separation Po= 2 W; fi= 1 kHz; RL=4Ω40 50 −dB
VOO DC output offset voltage VP= 14.4 V; on condition −0 100 mV
VP= 14.4 V; RL=4Ω;
mute condition −10 20 mV
Vn(o) noise output voltage on Rs=1kΩ; VP= 14.4 V; note 3 −80 150 µV
Vn(o)(mute) noise output voltage mute note 3 −020µV
V
o(mute) output voltage mute Vi(rms) =1V −3 500 µV
SVRR supply voltage ripple rejection Rs=0Ω; fi= 1 kHz;
Vripple = 2 V (p-p)
on condition 43 47 −dB
mute condition 55 70 −dB
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT