Philips TDA8950 , 13.4 External clock

TDA8950_1 © NXP B.V. 2008. All rights reserved.

Preliminary data sheet Rev. 01 — 9 September 2008 18 of 39

NXP Semiconductors TDA8950

2× 150 W class-D power ampliﬁer

13.3.2 Bridge-Tied Load (BTL)

Maximum output power:

(3)

Maximum current internally limited to 9.2 A:

(4)

Variables:

•RL: load impedance

•RsL: series impedance of the ﬁlter coil

•RDSon(hs): high-side RDSon of power stage output DMOS (temperature dependent)

•RDSon(ls): low-side RDSson of power stage output DMOS (temperature. dependent)

•fosc: oscillator frequency

•tmin: minimum pulse width (typical 150 ns, temp. dependent)

•VP: single-sided supply voltage (or 0.5 ×(VDD + |VSS|))

•Po(0.5 %): output power at the onset of clipping

Note that Io(peak)M should be below 9.2 A (Section 8.3.2). Io(peak) is the sum of the current

through the load and the ripple current. The value of the ripple current is dependent on the

coil inductance and voltage drop over the coil.

13.4 External clock

For duty cycle independent operation of the device, the external clock input frequency is

internally divided by two. This implies that the frequency of the external clock is as twice

as high as the internal clock (typical 2 × 345 kHz = 690 kHz).

If two or more class-D ampliﬁers are used it is recommended that all devices run at the

same switching frequency. This can be realized by connecting all OCS pins together and

feeding them from an external oscillator. When applying an external oscillator, it is

necessary to force pin OSC to a DC level above SGND. The internal oscillator is disabled

and the PWM modulator will switch with half the externally applied frequency.

The internal oscillator requires an external resistor Rext(OSC) and capacitor COSC between

pin OSC and PIN VSSA.

The noise contribution of the internal oscillator is supply voltage dependent. An external

low noise oscillator is recommended for low noise applications running at high supply

voltage.

Po 0.5%()

RL

RLRDSon hs() Rdson ls()

++

------------------------------------------------------------------2VP1t

min 0.5 f osc

×–()×× 2

2RL

--------------------------------------------------------------------------------------------------------------------------------------------------

=

Iopeak()

2VP1t

min 0.5 f osc

×–()×

RLRDSon hs() RDSon ls()

+()2RsL

++

-------------------------------------------------------------------------------------------

=

Contents

Main 1. General description 2. Features 3. Applications TDA8950 Rev. 01 9 September 2008 Preliminary data sheet 2 150 W class-D power amplier 2 150 W class-D power amplier 4. Quick reference data 5. Ordering information Preliminary data sheet Rev. 01 9 September 2008 3 of 39 6. Block diagram n.c. VSSA VSSD n.c. IN2M 7. Pinning information 7.1 Pinning TDA8950TH Fig 2. Pin conguration TDA8950TH Fig 3. Pin conguration TDA8950J NXP Semiconductors TDA8950 8. Functional description 8.1 General Fig 5. Timing on mode selection input Page NXP Semiconductors TDA8950 8.3.2 OverCurrent Protection (OCP) 8.3.3 Window Protection (WP) 8.3.4 Supply voltage protections 8.4 Differential audio inputs 9. Limiting values 10. Thermal characteristics In accordance with the Absolute Maximum Rating System (IEC 60134). 11. Static characteristics = 25 = 35 V; f = 345 kHz; T 12. Dynamic characteristics 12.1 Switching characteristics = 25 = 35 V; T 12.2 Stereo and dual SE application characteristics = 25 < 0.1 = 4 = 12.3 Mono BTL application characteristics = 25 < 0.1 = 8 = 13. Application information 13.1 Mono BTL application 13.2 Pin MODE 13.3 Output power estimation 13.3.1 SE 13.4 External clock 13.5 Noise 13.6 Heatsink requirements 13.7 Output current limiting Page Fig 10. Simplied application diagram TDA8950J 13.10 Layout and grounding 13.11 Curves measured in reference design VP = 35 V, 2 4 SE conguration. (1) OUT2, fi = 6 kHz (2) OUT2, fi = 1 kHz (3) OUT2, fi = 100 Hz Fig 13. THD as a function of output power, SE conguration with 2 6 load Fig 12. THD as a function of output power, SE conguration with 2 4 load VP = 35 V, 2 6 SE conguration. (1) OUT2, fi = 6 kHz (2) OUT2, fi = 1 kHz (3) OUT2, fi = 100 Hz Fig 14. THD as a function of output power, BTL conguration with 1 8 load VP = 35 V, 2 4 SE conguration. (1) OUT2, PO = 1 W (2) OUT2, PO = 10 W Fig 15. THD as a function of frequency, SE conguration with 2 4 load VP = 35 V, 2 6 SE conguration. (1) OUT2, Po = 1 W (2) OUT2, Po = 10 W Fig 16. THD as a function of frequency, SE conguration with 2 6 load VP = 35 V, 1 8 BTL conguration (1) Po = 1 W (2) Po = 10 W Fig 17. THD as a function of frequency, BTL conguration with 1 8 load VP = 35 V, 2 4 SE conguration For OUT1 and OUT2 for both 1 W and 10 W. Fig 18. Channel separation as a function of frequency, SE conguration with 2 4load VP = 35 V, 2 6 SE conguration For OUT1 and OUT2 for both 1 W and 10 W. Fig 19. Channel separation as a function of frequency, SE conguration with 2 6load Fig 20. Power dissipation as function of output power per channel Fig 21. Efciency as function of output power per channel Fig 22. Output power as a function of supply voltage, SE conguration Fig 23. Output power as function of supply voltage, BTL conguration Fig 24. Gain as function of frequency, Rs = 0 , Ci = 330 pF Fig 25. SVRR as function of ripple frequency Fig 26. SVRR as function of ripple frequency VP = 35 V (1) Out1, down (2) Out1, up Fig 27. Output voltage as function of mode voltage VP = 35 V, Vi = 2 V (rms), fosc = 325 kHz (1) OUT2, 8 (2) OUT2, 6 (3) OUT2, 4 Fig 28. Mute attenuation as function of frequency 14. Package outline Fig 29. Package outline SOT411-1 (DBS23P) DBS23P: plastic DIL-bent-SIL power package; 23 leads (straight lead length 3.2 mm) SOT411-1 Fig 30. Package outline SOT566-3 (HSOP24) HSOP24: plastic, heatsink small outline package; 24 leads; low stand-off height SOT566-3 15. Soldering of SMD packages 15.4 Reow soldering For further information on temperature proles, refer to Application Note 16. Revision history AN10365 Surface mount reow soldering description . 17. Legal information 17.1 Data sheet status 17.2 Denitions 17.3 Disclaimers 17.4 Trademarks 19. Contents