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Philips TDA8950 12.3 Mono BTL application characteristics

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TDA8950_1 © NXP B.V. 2008. All rights reserved.

Preliminary data sheet Rev. 01 — 9 September 2008 16 of 39

NXP Semiconductors TDA8950

2× 150 W class-D power ampliﬁer

12.3 Mono BTL application characteristics

[1] RsL is the series resistance of inductor of low-pass LC ﬁlter in the application.

[2] Output power is measured indirectly; based on RDSon measurement. See also Section 13.3.

[3] Total harmonic distortion is measured in a bandwidth of 22 Hz to 20 kHz, using an AES17 20 kHz brickwall

ﬁlter. Maximum limit is guaranteed but may not be 100 % tested.

[4] Vripple = Vripple(max) = 2 V (p-p); Rs = 0 Ω.

[5] B = 22 Hz to 20 kHz, using an AES17 20 kHz brickwall ﬁlter. Low noise due to BD modulation.

[6] B = 22 Hz to 20 kHz, using an AES17 20 kHz brickwall ﬁlter; independent of Rs.

[7] Vi = Vi(max) = 1 V (RMS); fi = 1 kHz.

Table 10. Dynamic characteristics

V

P

=

±

35 V; R

L

= 8

Ω

; f

i

= 1 kHz; f

osc

= 345 kHz; R

sL

< 0.1

Ω

[1]

; T

amb

= 25

°

C; unless otherwise

speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Pooutput power L = 22 µH; C = 680 nF;

Tj=85°C; RL=8Ω

[2]

THD = 10 %; VP=±39 V - 340 - W

THD = 10 %; VP=±37 V - 300 - W

THD = 0.5 %; VP=±37 V - 200 - W

THD total harmonic

distortion Po= 1 W; fi= 1 kHz [3] - 0.05 - %

Po= 1 W; fi= 6 kHz [3] - 0.05 - %

Gv(cl) closed-loop voltage

gain -36-dB

SVRR supply voltage ripple

rejection between pin VDDPn and

SGND

operating; fi= 100 Hz [4] -80-dB

operating; fi= 1 kHz [4] -80-dB

mute; fi= 100 Hz [4] -95-dB

standby; fi= 100 Hz [4] - 120 - dB

between pin VSSPn and

SGND

operating; fi= 100 Hz [4] -75-dB

operating; fi= 1 kHz [4] -75-dB

mute; fi= 100 Hz [4] -90-dB

standby; fi= 100 Hz [4] - 130 - dB

Ziinput impedance measured between the input

pins and SGND 45 63 - kΩ

Vn(o) output noise voltage operating; Rs=0Ω[5] - 190 - µV

mute [6] -45-µV

αmute mute attenuation fi= 1 kHz; Vi= 2 V (RMS) [7] -82-dB

CMRR common mode

rejection ratio Vi(CM) = 1 V (RMS) - 75 - dB

Contents

Main 1. General description 2. Features 3. Applications TDA8950 Rev. 01 9 September 2008 Preliminary data sheet 2 150 W class-D power amplier 2 150 W class-D power amplier 4. Quick reference data 5. Ordering information Preliminary data sheet Rev. 01 9 September 2008 3 of 39 6. Block diagram n.c. VSSA VSSD n.c. IN2M 7. Pinning information 7.1 Pinning TDA8950TH Fig 2. Pin conguration TDA8950TH Fig 3. Pin conguration TDA8950J NXP Semiconductors TDA8950 8. Functional description 8.1 General Fig 5. Timing on mode selection input Page NXP Semiconductors TDA8950 8.3.2 OverCurrent Protection (OCP) 8.3.3 Window Protection (WP) 8.3.4 Supply voltage protections 8.4 Differential audio inputs 9. Limiting values 10. Thermal characteristics In accordance with the Absolute Maximum Rating System (IEC 60134). 11. Static characteristics = 25 = 35 V; f = 345 kHz; T 12. Dynamic characteristics 12.1 Switching characteristics = 25 = 35 V; T 12.2 Stereo and dual SE application characteristics = 25 < 0.1 = 4 = 12.3 Mono BTL application characteristics = 25 < 0.1 = 8 = 13. Application information 13.1 Mono BTL application 13.2 Pin MODE 13.3 Output power estimation 13.3.1 SE 13.4 External clock 13.5 Noise 13.6 Heatsink requirements 13.7 Output current limiting Page Fig 10. Simplied application diagram TDA8950J 13.10 Layout and grounding 13.11 Curves measured in reference design VP = 35 V, 2 4 SE conguration. (1) OUT2, fi = 6 kHz (2) OUT2, fi = 1 kHz (3) OUT2, fi = 100 Hz Fig 13. THD as a function of output power, SE conguration with 2 6 load Fig 12. THD as a function of output power, SE conguration with 2 4 load VP = 35 V, 2 6 SE conguration. (1) OUT2, fi = 6 kHz (2) OUT2, fi = 1 kHz (3) OUT2, fi = 100 Hz Fig 14. THD as a function of output power, BTL conguration with 1 8 load VP = 35 V, 2 4 SE conguration. (1) OUT2, PO = 1 W (2) OUT2, PO = 10 W Fig 15. THD as a function of frequency, SE conguration with 2 4 load VP = 35 V, 2 6 SE conguration. (1) OUT2, Po = 1 W (2) OUT2, Po = 10 W Fig 16. THD as a function of frequency, SE conguration with 2 6 load VP = 35 V, 1 8 BTL conguration (1) Po = 1 W (2) Po = 10 W Fig 17. THD as a function of frequency, BTL conguration with 1 8 load VP = 35 V, 2 4 SE conguration For OUT1 and OUT2 for both 1 W and 10 W. Fig 18. Channel separation as a function of frequency, SE conguration with 2 4load VP = 35 V, 2 6 SE conguration For OUT1 and OUT2 for both 1 W and 10 W. Fig 19. Channel separation as a function of frequency, SE conguration with 2 6load Fig 20. Power dissipation as function of output power per channel Fig 21. Efciency as function of output power per channel Fig 22. Output power as a function of supply voltage, SE conguration Fig 23. Output power as function of supply voltage, BTL conguration Fig 24. Gain as function of frequency, Rs = 0 , Ci = 330 pF Fig 25. SVRR as function of ripple frequency Fig 26. SVRR as function of ripple frequency VP = 35 V (1) Out1, down (2) Out1, up Fig 27. Output voltage as function of mode voltage VP = 35 V, Vi = 2 V (rms), fosc = 325 kHz (1) OUT2, 8 (2) OUT2, 6 (3) OUT2, 4 Fig 28. Mute attenuation as function of frequency 14. Package outline Fig 29. Package outline SOT411-1 (DBS23P) DBS23P: plastic DIL-bent-SIL power package; 23 leads (straight lead length 3.2 mm) SOT411-1 Fig 30. Package outline SOT566-3 (HSOP24) HSOP24: plastic, heatsink small outline package; 24 leads; low stand-off height SOT566-3 15. Soldering of SMD packages 15.4 Reow soldering For further information on temperature proles, refer to Application Note 16. Revision history AN10365 Surface mount reow soldering description . 17. Legal information 17.1 Data sheet status 17.2 Denitions 17.3 Disclaimers 17.4 Trademarks 19. Contents