Main
1. General description
2. Features
3. Applications
TDA8950
Rev. 01 9 September 2008 Preliminary data sheet
2 150 W class-D power amplier
2 150 W class-D power amplier
4. Quick reference data
5. Ordering information
Preliminary data sheet Rev. 01 9 September 2008 3 of 39
6. Block diagram
n.c.
VSSA
VSSD n.c.
IN2M
7. Pinning information
7.1 Pinning
TDA8950TH
Fig 2. Pin conguration TDA8950TH Fig 3. Pin conguration TDA8950J
NXP Semiconductors TDA8950
8. Functional description
8.1 General
Fig 5. Timing on mode selection input
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NXP Semiconductors TDA8950
8.3.2 OverCurrent Protection (OCP)
8.3.3 Window Protection (WP)
8.3.4 Supply voltage protections
8.4 Differential audio inputs
9. Limiting values
10. Thermal characteristics
In accordance with the Absolute Maximum Rating System (IEC 60134).
11. Static characteristics
= 25
=
35 V; f
= 345 kHz; T
12. Dynamic characteristics
12.1 Switching characteristics
= 25
=
35 V; T
12.2 Stereo and dual SE application characteristics
= 25
< 0.1
= 4
=
12.3 Mono BTL application characteristics
= 25
< 0.1
= 8
=
13. Application information
13.1 Mono BTL application
13.2 Pin MODE
13.3 Output power estimation
13.3.1 SE
13.4 External clock
13.5 Noise
13.6 Heatsink requirements
13.7 Output current limiting
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Fig 10. Simplied application diagram
TDA8950J
13.10 Layout and grounding
13.11 Curves measured in reference design
VP = 35 V, 2 4 SE conguration. (1) OUT2, fi = 6 kHz (2) OUT2, fi = 1 kHz (3) OUT2, fi = 100 Hz
Fig 13. THD as a function of output power, SE conguration with 2 6 load
Fig 12. THD as a function of output power, SE conguration with 2 4 load
VP = 35 V, 2 6 SE conguration. (1) OUT2, fi = 6 kHz (2) OUT2, fi = 1 kHz (3) OUT2, fi = 100 Hz
Fig 14. THD as a function of output power, BTL conguration with 1 8 load
VP = 35 V, 2 4 SE conguration. (1) OUT2, PO = 1 W (2) OUT2, PO = 10 W
Fig 15. THD as a function of frequency, SE conguration with 2 4 load
VP = 35 V, 2 6 SE conguration. (1) OUT2, Po = 1 W (2) OUT2, Po = 10 W
Fig 16. THD as a function of frequency, SE conguration with 2 6 load
VP = 35 V, 1 8 BTL conguration (1) Po = 1 W (2) Po = 10 W
Fig 17. THD as a function of frequency, BTL conguration with 1 8 load
VP = 35 V, 2 4 SE conguration For OUT1 and OUT2 for both 1 W and 10 W.
Fig 18. Channel separation as a function of frequency, SE conguration with 2 4load
VP = 35 V, 2 6 SE conguration For OUT1 and OUT2 for both 1 W and 10 W.
Fig 19. Channel separation as a function of frequency, SE conguration with 2 6load
Fig 20. Power dissipation as function of output power per channel
Fig 21. Efciency as function of output power per channel
Fig 22. Output power as a function of supply voltage, SE conguration
Fig 23. Output power as function of supply voltage, BTL conguration
Fig 24. Gain as function of frequency, Rs = 0 , Ci = 330 pF
Fig 25. SVRR as function of ripple frequency
Fig 26. SVRR as function of ripple frequency
VP = 35 V (1) Out1, down (2) Out1, up
Fig 27. Output voltage as function of mode voltage
VP = 35 V, Vi = 2 V (rms), fosc = 325 kHz (1) OUT2, 8 (2) OUT2, 6 (3) OUT2, 4
Fig 28. Mute attenuation as function of frequency
14. Package outline
Fig 29. Package outline SOT411-1 (DBS23P)
DBS23P: plastic DIL-bent-SIL power package; 23 leads (straight lead length 3.2 mm) SOT411-1
Fig 30. Package outline SOT566-3 (HSOP24)
HSOP24: plastic, heatsink small outline package; 24 leads; low stand-off height SOT566-3
15. Soldering of SMD packages
15.4 Reow soldering
For further information on temperature proles, refer to Application Note
16. Revision history
AN10365 Surface mount reow soldering description
.
17. Legal information
17.1 Data sheet status
17.2 Denitions
17.3 Disclaimers
17.4 Trademarks
19. Contents
