1999 May 10 10
Philips Semiconductors Preliminary specification
Universal Serial Bus (USB) CODEC UDA1325
Memory Management Unit (MMU) and integrated RAM
The MMU and integrated RAM handle the temporary data
storage of all USB packets that are received or sent over
the bus.
The MMU and integrated RAM handle the differences
between data rate of the USB and the application allowing
the microcontroller to read and write USB packets at its
own speed.
The audio data is transferred via an isochronous data sink
endpoint or source endpoint and is stored directly into the
RAM. Consequently, no handshaking mechanism is used.
Audio Sample Redistribution (ASR)
The ASR reads the audio samples from the MMU and
integrated RAM and distributes these samples equidistant
over a 1 ms frame period. The distributed audio samples
are translated by the digital I/O module to standard I2S-bus
format or 16, 18 or 20 bits LSB-justified I2S-bus format.
The ASR generates the bit clock output (BCKO) and the
Word Select Output signal (WSO) of the I2S output.
The 80C51 microcontroller
The microcontroller receives the control information
selected from the USB by the USB processor. It can be
used for handling the high-level USB protocols and the
user interfaces. The microcontroller does not handle the
audio stream.
The major task of the software process that is mapped
upon the microcontroller, is to control the different modules
of the UDA1325 in such a way that it behaves as a USB
device.
The embedded 80C51 microcontroller is compatible with
the 80C51 family of microcontrollers described in the
80C51 family single-chip 8-bit microcontrollers of “Data
Handbook IC20”, which should be read in conjunction with
this data sheet.
The internal ROM size is 12 kbyte. The internal RAM size
is 256 byte. A Watchdog Timer is not integrated.
The Analog-to-Digital Interface (ADIF)
The ADIF is used for sampling an analog input signal from
a microphone or line input and sending the audio samples
to the USB interface. The ADIF consists of a stereo
Programmable Gain Amplifier (PGA), a stereo
Analog-to-Digital Converter (ADC) and Decimation Filters
(DFs). The sample frequency of the ADC is determined by
the ADC clock (see Section “The clock source of the
analog-to-digital interface”). The user can also select a
digital serial input instead of an analog input. In this event
the sample frequency is determined by the continuous WS
clock with a range between 5 to55 kHz. Digital serial input
is possible with four formats (I2S-bus, 16, 18 or 20 bits
LSB-justified).
Programmable Gain Amplifier circuit (PGA)
This circuit can be used for a microphone or line input.
The input audio signals can be amplified by seven different
gains (−3 dB, 0dB, 3 dB, 9 dB, 15dB, 21 dBand 27 dB).
The gain settings are given in Table 17.
The Analog-to-Digital Converter (ADC)
The stereo ADC of the UDA1325 consists of two 3rd-order
Sigma-Delta modulators. They have a modified
Ritchie-coder architecture in a differential switched
capacitor implementation. The oversampling ratio is 128.
Both ADCs can be switched off in power saving mode (left
and right separate). The ADC clock is generated by the
analog PLL or the ADC oscillator.
The Decimation Filter (DF)
The decimator filter converts the audio data from 128fs
down to 1fs with a word width of 8, 16or 24 bits. This data
can be transmitted over the USB as mono or stereo in
1, 2 or 3 bytes/sample. The decimator filters are clocked
by the ADC clock.