1999 May 10 41
Philips Semiconductors Preliminary specification
Universal Serial Bus (USB) CODEC UDA1325
SDA and SCL lines for 100 kHz I2C devices
fSCL SCL clock frequency 0 −100 kHz
tBUF bus free time between a STOP and
START condition 4.7 −−µs
t
HD;STA hold time (repeated) START
condition 4.0 −−µs
t
LOW LOW period of the SCL clock 4.7 −−µs
t
HIGH HIGH period of the SCL clock 4.0 −−µs
t
SU;STA set-up time for a repeated START
condition 4.7 −−µs
t
SU;STO set-up time for STOP condition 4.0 −−µs
t
HD;DAT data hold time 5.0 −−µs
t
SU;DAT data set-up time 250 −−ns
trrise time of both SDA and SCL
signals
−−1000 ns
tffall time of both SDA and SCL
signals
−−300 ns
CL(bus) capacitive load for each bus line −−400 pF
Oscillator 1 (system clock)
fosc oscillator frequency −48 −MHz
δduty factor −50 −%
gmtransconductance 12.8 22.1 30.2 mS
Rooutput resistance 0.6 1.1 2.3 kΩ
Ci(XTAL1a) parasitic input capacitance XTAL1a 4.5 4.8 5.2 pF
Ci(XTAL2a) parasitic input capacitance XTAL2a 4.1 4.6 5.0 pF
Istart start-up current 3.7 7.6 13.0 mA
Oscillator 2 (for ADC clock)
fosc oscillator frequency 8.192 −14.08 MHz
δduty cycle −50 −%
gmtransconductance 8.1 13.6 18.1 mA/V
Rooutput resistance 1.3 2.0 4.0 kΩ
Ci(XTAL1b) parasitic input capacitance XTAL1b 5.0 5.4 5.7 pF
Ci(XTAL2b) parasitic input capacitance XTAL2b 4.1 4.6 5.0 pF
Istart start-up current 2.4 5.0 8.4 mA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT