1999 May 10 28
Philips Semiconductors Preliminary specification
Universal Serial Bus (USB) CODEC UDA1325
Table 23 ASR control register
START-UP BEHAVIOUR AND POWER MANAGEMENT
Start-up of the UDA1325
After power-on (of VDDA1), an internal Power-on reset signal becomes HIGH after a certain RC time. This RC time is
created by using the internal resistor (2 ×50 kΩ) divider for creating the reference voltage for the FSDAC in combination
with the capacitor connected externally to the VREFDA pin. The FSDAC and the internal resistor divider are supplied by
VDDA1 and VSSA1. The RC time can be calculated using R = 25000 Ω and C = Cref.
During 20 ms after Power-on reset becomes HIGH the UDA1325 has to initiate the internal registers. During this
initialisation, the user should prevent indicating the ‘connected’ status to the USB-host. This can be done by forcing the
DP-line LOW (i.e. via one of the GP pins).
Power Management
The total current drawn from the USB supply (for i.e. bus-powered operation of the UDA1325 application) must be less
than 500 µA in suspend mode. In order to reach that low current target, the total power dissipation of the UDA1325 can
be reduced by disabling all internal clocks and switching off all internal analog modules.
Important note: In order to make use of power reduction (Power-down mode) and be able to restart after power-down, a
number of precautions must be taken!
ADDRESS REGISTER COMMENTS BIT VALUE
2000h ASR control register robust word clock 7 0 = off (not recommended)
1 = on (recommended)
serial I2S-bus output format
digital I/O interface 6and 5 00 = I2S-bus
01 = 16-bit LSB justified
10 = 18-bit LSB justified
11= 20-bit LSB justified
phase inversion (on right mono
output) 4 0 = mono phase inversal off
1 = mono phase inversal on
bits per sample modi 3 and 2 00 = reserved
01 = 8-bit audio
10 = 16-bit audio
11= 24-bit audio
mono or stereo operation 1 0= mono
1 = stereo
ASR register start-up mode 0 0 = stop (e.g. at alternate
setting with bandwidth equal to
zero)
1=go