Quatech DSCLP/SSCLP-100 user manual Address Map and Special Registers, Port, I/O Address Range

4 Address Map and Special Registers

This chapter explains how the two UARTs and special registers are

addressed, as well as the layout of those registers. This material will be of interest to programmers writing driver software for the DSCLP-100.

4.1 Base Address and Interrupt Level (IRQ)

The base address and IRQ used by the DSCLP-100 are determined by the BIOS or operating system. Each serial port uses 8 consecutive I/O locations. The two ports reside in a single block of I/O space in eight byte increments, for a total of 16 contiguous bytes, as shown in Figure 6.

Port	I/O Address Range
Serial 1	Base Address + 0	to	Base Address + 7
Serial 2	Base Address + 8	to	Base Address + 15

Figure 6 --- Port Address Map

All serial ports share the same IRQ. The DSCLP-100 signals a hardware interrupt when any port requires service. The interrupt signal is maintained until no port requires service. Interrupts are level-sensitive on the PCI bus.

The base address and IRQ are automatically detected by the device drivers Quatech supplies for various operating systems. For cases where no device driver is available, such as for operation under DOS, Quatech supplies the "QTPCI"

DOS software utility for manually determining the resources used. See section 6.3.1 for details.

10 DSCLP/SSCLP-100 User's Manual