Renesas M34282T5-OPT 5. Precautions to Be Taken When Debugging

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5. Precautions to Be Taken When Debugging

The M34282T5-OPT can be reset by the reset command of emulator debugger RTT72, but cannot

emulate device operation at power-on reset. Use an evaluation MCU (OTP version) to verify the

operation associated with power-on reset.

The M34282T5-OPT is equipped with the M34282E2GP as an evaluation MCU. The RAM and

ROM areas that can be referenced by emulator debugger RTT72 are specified by switches SW2 and

SW3 as listed in Table 5.1.

Table 5.1 Memory areas that can be referenced by emulator debugger RTT72

Figure 5.1 Output waveform of check pin TP4

WRST

System clock XIN

*Addresses in the RAM area are shown as described below according to the data pointer registers

X and Y.

Example: RAM address XXh

Y (Y = 0 to B, or Y = 0 to F)

X (X = 0 to 3)

With the M34282T5-OPT, the watchdog timer cannot be operated. Therefore use an evaluation MCU

(OTP version) to verify the operation associated with the watchdog timer function.

And with the M34282T5-OPT, when executing WRST instruction, the check pin TP4 outputs "H"

level (see Figure 5.1), so you can check the initializing cycle of the watchdog timer by monitoring

the pulse width frequency of TP4.

Switch setting

SW3 SW2 RAM area ROM area

00h - 0Bh

10h - 1Bh

20h - 2Bh

30h - 3Bh

(4 bits x 48 words) 000h - 3FFh

(9 bits x 1024 words)

000h - 7FFh

(9 bits x 2048 words)

00h - 3Fh (4 bits x 64 words)

"H"

"L"