3. IC902 (H Driver) and IC904 (V Driver)

An H driver (IC902) and V driver (IC904) are necessary in order to generate the clocks (vertical transfer clock, horizontal transfer clock and electronic shutter clock) which driver the CCD.

IC902 is an inverter IC which drives the horizontal CCDs (H1 and H2). In addition the XV1-XV4 signals which are output from Pins (166), (167), (169) and (171) of IC102 are the vertical transfer clocks, and the XSG1 and XSG2 signals which is output from Pins (168) and (170) of IC102 is superimposed onto XV1 and XV3 at IC904 in order to generate a ternary pulse. In addition, the XSUB signal which is output from Pin

(165)of IC102 is used as the sweep pulse for the electronic shutter, and the RG signal which is output from Pin (159) of IC102 is the reset gate clock.

1A

1

14

VCC

1Y

2

13

6A

2A

3

12

6Y

2Y

4

11

5A

3A

5

10

5Y

3Y

6

9

4A

GND 7

8

4Y

Fig. 1-2. IC902 Block Diagram

1 CPP3

CPP1 20

 

VH

Change Pump

2

CPP2 19

 

 

+

 

 

-

3

DCIN

DC OUT 18

4

XSHT

VSHT 17

5

XV2

VL 16

6

XV1

Vφ2 15

7

XSG1

Vφ1 14

8

XV3

VM 13

9

XSG2

Vφ3 12

10 XV4

Vφ4 11

4.IC905 (CDS, AGC Circuit and A/D converter)

The video signal which is output from the CCD is input to Pins (26) and (27) of IC905. There are S/H blocks inside IC905 generated from the XSHP and XSHD pulses, and it is here that CDS (correlated double sampling) is carried out.

After passing through the CDS circuit, the signal passes through the AGC amplifier. It is A/C converted internally into a 10-bit signal, and is then input to IC102 of the CA2 circuit board. The gain of the AGC amplifier is controlled by the volt- age at pin (29) which is output from IC102 of the CA2 circuit board and smoothed by the PWM.

PBLK CLPDM PGACONT1 PGACONT2 SHP SHD ADCCLK

19

23

29

30

21

22

16

 

CLAMP

 

 

 

TIMING

 

 

 

 

 

PGA

GENERATOR

PIN 27

 

 

 

 

 

 

CDS

 

 

 

 

 

10 2 DOUT

DIN 26

 

 

 

 

 

 

 

 

MUX

S/H

A/D

ADCIN 36

 

 

 

 

 

 

 

11

 

 

 

 

 

 

 

 

 

 

 

 

CLAMP

 

 

 

12 DRVDD

 

REFERENCE

 

AD9802

17 DVDD

37

48

47

18

20

41

33

 

43

CMLEVEL VRT VTB STBY CLPOB ADCMODE ACVDD ADVDD

Fig. 1-4. IC905 Block Diagram

Fig. 1-3. IC904 Block Diagram

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