Silicon Image SSD-C08G(I)-3150 manual Reg, Dmack, Reset, +5V, +3.3V power PC Card memory Mode

ELECTRICAL SPECIFICATION				SSD-CXXX(I)-3150 DATA SHEET
	Table 8: Signal Descriptions (Continued)
	Signal Name	Pin	Type	Description
	-REG	44	I	This signal is used during memory
	(PC Card memory			cycles to distinguish between
	mode)			common memory and register
	Attribute Memory			(attribute) memory accesses. This
				signal is set:
	Select
				• High for common memory.
				• Low for attribute memory.
	-REG			The signal must also be active (low)
	(PC Card I/O			during I/O cycles when the I/O
	mode)			address is on the bus.
	-DMACK			In true IDE mode, this signal is used
	(True IDE mode)			by the host in response to DMARQ to
				initiate DMA transfers. The DMARQ/
				-DMACK handshake is used to
				provide flow control during the
				transfer. When -DMACK is asserted,
				-CS0 and -CS1 are not asserted and
				transfers are 16-bits wide.
	-RESET	41	I	When the pin is high, this signal
	(PC Card memory			resets the SiliconDrive CF. The
	mode)			SiliconDrive CF is reset only at power-
				up if this pin is left high or open from
				power-up. The SiliconDrive CF is also
				reset when the Soft Reset bit in the
				Card Configuration Option register is
				set.
	-RESET			This signal is the same as the PC
	(PC Card I/O			Card Memory Mode signal.
	mode)
	-RESET			In the true IDE mode, this input pin is
	(True IDE mode)			the active low hardware reset from the
				host.
	VCC	13, 38	-	+5V, +3.3V power.
	(PC Card memory
	mode)

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3150C-10DSR PAGE 12 FEBRUARY 2, 2009