ELECTRICAL SPECIFICATION

SSD-PXXX(I)-3100 DATA SHEET

I/O Access Write Timing

A[10::0]

 

 

 

 

tRLIGL

 

tAXIGH

____

 

 

 

 

tRHIGH

REG

 

 

 

 

 

__

tCLIGL

 

tCHIGH

 

 

 

 

 

CE

 

 

 

_____

 

tIGLIGH

 

 

 

 

IOWR

tAVIGL

 

tAXISH

 

 

______

tAVISL

 

 

IOIS16

 

 

 

 

 

 

 

tIGHQX

tIGHDX

 

 

 

D[15::0]

 

 

 

Figure 5: I/O Access Write Timing Diagram

Table 15: I/O Access Write Timing

Symbol

Parameter

Minimum

Maximum

Units

tIGHDX

Data Hold following IOWR

5

-

ns

tIGHQX

Data Setup before IOWR

20

-

ns

tIGLIGH

IOWR Pulse Width

65

-

ns

tAVIGL

Address Setup before IOWR

25

-

ns

tAXIGH

Address Hold following IOWR

10

-

ns

tCLIGL

CE Setup before IOWR

5

-

ns

tCHIGH

CE Hold following IOWR

10

-

ns

tRLIGL

REG Setup before IOWR

5

-

ns

tRHIGH

REG Hold following IOWR

0

-

ns

tAVISL

IOIS16 Delay Falling from Address

-

(1)

ns

tAXISH

IOIS16 Delay Rising from Address

-

(1)

ns

Note: (1) IOIS16 and INPACK are not supported.

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3100P-06DSR

PAGE 20

FEBRUARY 2, 2009

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Silicon Image SSD-P16G(I)-3100 manual O Access Write Timing