ATA AND TRUE IDE REGISTER DECODING

SSD-PXXX(I)-3100 DATA SHEET

PRIMARY AND SECONDARY I/O MAPPED REGISTER DECODING

Table 32: Primary and Secondary I/O Mapped Register Decoding

Reg#

A10

A9:A4

A9:A4

A3

A2

A1

A0

IORD# = L

IOWR# = L

Primary

Secondary

 

 

 

 

 

 

 

 

 

 

0

X

1Fxh

17xh

0

0

0

0

Even Data

Even Data

 

 

 

 

 

 

 

 

Read

Write

 

 

 

 

 

 

 

 

 

 

0

X

1Fxh

17xh

0

0

0

1

Error

Feature

 

 

 

 

 

 

 

 

 

 

0

X

1Fxh

17xh

0

0

1

0

Sector

Sector

 

 

 

 

 

 

 

 

Count

Count

 

 

 

 

 

 

 

 

 

 

0

X

1Fxh

17xh

0

0

1

1

Sector

Sector

 

 

 

 

 

 

 

 

Number

Number

 

 

 

 

 

 

 

 

 

 

0

X

1Fxh

17xh

0

1

0

0

Cylinder

Cylinder

 

 

 

 

 

 

 

 

Low

Low

 

 

 

 

 

 

 

 

 

 

0

X

1Fxh

17xh

0

1

0

1

Cylinder

Cylinder

 

 

 

 

 

 

 

 

High

High

 

 

 

 

 

 

 

 

 

 

0

X

1Fxh

17xh

0

1

1

0

Drive/Head

Drive/Head

 

 

 

 

 

 

 

 

 

 

0

X

1Fxh

17xh

0

1

1

1

Status

Command

 

 

 

 

 

 

 

 

 

 

0

X

3Fxh

37xh

0

1

1

0

Alternate

Device

 

 

 

 

 

 

 

 

Status

Control

 

 

 

 

 

 

 

 

 

 

0

X

3Fxh

37xh

0

1

1

1

Drive

Reserved

 

 

 

 

 

 

 

 

Address

 

 

 

 

 

 

 

 

 

 

 

SILICONSYSTEMS PROPRIETARY

This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.

All unauthorized use and/or reproduction is prohibited.

3100P-06DSR

PAGE 45

FEBRUARY 2, 2009

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Image 55
Silicon Image SSD-P16G(I)-3100 manual Primary and Secondary I/O Mapped Register Decoding, Reg# A10 A9A4, Primary Secondary