ARCNET 5 Port HUB Controller
Datasheet
DESCRIPTION OF PIN FUNCTIONS
PIN NO. | NAME | INPUT/OUTPUT | DESCRIPTION | NOTE |
1 | TXENB1 | OUTPUT | Port |
|
|
|
| Setting for traffic release time (It should |
|
2 | HM | INPUT | be open for normal operation.) | |
|
|
| Port EXT. Polar assignment for EXTRX |
|
3 | SE | INPUT | input (0:active Hi, 1:active Low) | |
4 | NC |
| Reserved. It should be open. |
|
|
|
| Port EXT. Polar assignment of EXTTX |
|
5 | LE | INPUT | output (0:active Low, 1:active Hi) | |
|
|
| Port EXT. |
|
6 | EXTRX | INPUT | transceiver. | |
|
|
| Port EXT. Output mode assignment of |
|
|
|
| EXTTX (0:pulse output, 1:Tx control |
|
7 | ME | INPUT | output) | |
8 | VSS1 |
| Ground |
|
9 | EXTTX | OUTPUT | Port EXT. Output to media transceiver. |
|
10 | VDD1 |
| Power Supply |
|
11 | CKO | OUTPUT | Clock Output |
|
12 | VSS2 |
| Ground |
|
13 | CKM2 | INPUT | Network speed (data rate) setting. | |
14 | CKM1 | INPUT |
| |
15 | CKM0 | INPUT |
| |
16 | NC |
| Reserved. It should be open. |
|
17 | RXFLT | INPUT | Test Pin. It should be open. | |
|
|
| Test Pin for PLL.. It should connected to |
|
18 | nPLLTST | INPUT | VDD (Set to high) |
|
19 | VDD2 |
| Power Supply |
|
20 | XTLI | INPUT | X'tal input/External clock input. |
|
21 | XTLO | OUTPUT | X'tal output |
|
22 | VSS4 |
| Ground |
|
23 | NC |
| Reserved. It should be open. |
|
24 | VDD4 |
| Power Supply |
|
25 | VDD3 |
| Power Supply |
|
26 | AVDD |
| Analog Power Supply |
|
27 | RO | OUTPUT | VCO output for internal PLL. |
|
|
|
| Connection pin to loop filter for internal |
|
28 | LP | OUTPUT | PLL. |
|
29 | AGS | INPUT | Analog sense pin for internal PLL. |
|
30 | AVSS |
| Analog Ground |
|
31 | VSS3 |
| Ground |
|
32 | VSS5 |
| Ground |
|
33 | NC |
| Reserved. It should be open. |
|
|
|
| Port EXT. |
|
34 | nEXTOD | INPUT | drain output, 1:normal output) | |
35 | nMBE | INPUT | Port EXT. Noise cut (0:on, 1:off) | |
36 | nMBB | INPUT | Port A0/A1 Noise cut (0:on, 1:off) | |
37 | nMBA | INPUT | Port B0/B1 Noise cut (0:on, 1:off) | |
|
|
| Port EXT. Jitters correct mode (0:big |
|
38 | nBJE | INPUT | jitters mode, 1:normal mode) | |
|
|
| Port A0/A1 Jitters correct mode (0:big |
|
39 | nBJB | INPUT | jitter mode, 1:normal mode) | |
|
|
| Port B0/B1 Jitter correct mode (0:big |
|
40 | nBJA | INPUT | jitter mode, 1:normal mode) | |
41 | VSS6 |
| Ground |
|
42 | nRST | INPUT | Internal reset signal (active Low) | |
43 | nCKOEN | INPUT | Enable of CKO output. | |
Revision 1.1 |
| Page 6 | SMSC |
DATASHEET