4th Generation USB 2.0 Flash Media Controller with Integrated Card Power FETs & HS Hub
Datasheet
Chapter 6 Pin DescriptionsThis section provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface.
The “n” or “_N” symbol in the signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When “n” is not present before the signal name (or “_N” after the signal name), the signal is asserted when at the high voltage level.
The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of “active low” and “active high” signal. The term assert, or assertion indicates that a signal is active, independent of whether that level is represented by a high or low voltage. The term negate, or negation indicates that a signal is inactive.
6.1PIN Descriptions
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NAME | SYMBOL |
| TYPE | DESCRIPTION |
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| UPSTREAM USB INTERFACE | ||
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USB Bus Data | USBUP_DM |
| These pins connect to the Upstream USB bus data | |
| USBUP_DP |
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| signals. |
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Detect Upstream | VBUS_DET |
| I/O12 | Detects state of Upstream VBUS power. The SMSC |
VBUS Power |
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| Hub monitors VBUS_DET to determine when to assert |
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| the internal D+ |
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| event). |
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| When designing a detachable hub, this pin must be |
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| connected to the VBUS power pin of the USB port that |
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| is upstream of the hub. |
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| For |
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| attached host, this pin must be |
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| or 5.0V (typically VDD33). |
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USB Bus Data | USBDN_DM |
| These pins connect to the Downstream USB bus data | |
| [4:2] |
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| signals. |
| USBDN_DP |
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| [4:2] |
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USB Power Enable | PRTPWR[4:2] |
| I/O12 | Enables power to USB peripheral devices |
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| (downstream). |
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| The active signal level of the PRTPWR[4:2] pins is |
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| determined by the Power Polarity Strapping function of |
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| the PRTPWR_POL pin. |
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Port Power Polarity | PRTPWR_POL |
| I/O12 | Port Power Polarity strapping determination for the |
Strapping |
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| active signal polarity of the PRTPWR[4:2] pins. |
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| While RESET_N is asserted, the logic state of this pin |
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| will (though the use of internal combinatorial logic) |
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| determine the active state of the PRTPWR[4:2] pins in |
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| order to ensure that downstream port power is not |
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| inadvertently enabled to inactive ports during a |
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| hardware reset. |
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| ‘1’ = PRTPWR[4:2] pins have an active ‘high’ polarity |
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| ‘0’ = PRTPWR[4:2] pins have an active ‘low’ polarity |
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Revision 1.6 | 14 | SMSC USB2601/USB2602 |
| DATASHEET |
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