4th Generation USB 2.0 Flash Media Controller with Integrated Card Power FETs & HS Hub
Datasheet
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NAME | SYMBOL | TYPE | DESCRIPTION |
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General Purpose | GPIO11/ | I/O8 | GPIO: These pins may be used either as input, edge |
I/O | CRD_PWR2 |
| sensitive interrupt input, or output. |
Or |
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| CRD_PWR: Card Power drive of 3.3V @ 200mA. | |
Card Power |
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General Purpose | GPIO[15:12] | I/O8 | These pins may be used either as input, or output. |
I/O |
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RESET input | RESET_N | IS | This active low signal is used by the system to reset the |
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| chip. The active low pulse should be at least 1μs wide. |
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TEST Input | TEST | IPD | Used for testing the IC. User must treat either as a no- |
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| connect, or connect to the ground. |
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USB Transceiver | RBIAS | I | A 12.0kΩ, ± 1.0% resistor is attached from VSS to this |
Bias |
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| pin, in order to set the transceiver’s internal bias |
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| currents. |
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Analog Test | ATEST | AIO | This signal is used for testing the analog section of the |
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| chip and should be connected to VDDA33 for normal |
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| operation. |
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Crystal | XTAL1/ | ICLKx | 24MHz Crystal or external clock input. |
Input/External Clock | CLKIN |
| This pin can be connected to one terminal of the crystal |
Input |
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| or can be connected to an external 24MHz clock when |
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| a crystal is not used. |
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| Note: The ‘SEL_CLKDRV and CLK_SEL[1:0]’ pins |
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| will be sampled while RESET_N is asserted, |
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| and the value will be latched upon RESET_N |
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| negation. This will determine the clock source |
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| and value. |
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Crystal Output | XTAL2 | OCLKx | 24MHz Crystal |
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| This is the other terminal of the crystal, or left open |
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| when an external clock source is used to drive |
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| XTAL1/CLKIN. It may not be used to drive any external |
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| circuitry other than the crystal circuit. |
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Select Clock Drive | SEL_CLKDRV | I/O8PD | SEL_CLKDRV. During RESET_N assertion, this pin will |
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| select the operating clock mode (crystal or externally |
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| driven clock source), and a weak |
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| enabled. When RESET_N is negated, the value will be |
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| internally latched and the internal |
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| disabled. |
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| ‘0’ = Crystal operation (24MHz) |
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| ‘1’ = Externally driven clock source (24MHz) |
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Clock Select | CLK_SEL[1:0] | I/O8PD | SEL[1:0]. During RESET_N assertion, these pins will |
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| select the operating frequency of the external clock, and |
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| the corresponding weak |
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| enabled. When RESET_N is negated, the value on |
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| these pins will be internal latched and the internal pull- |
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| downs will be disabled. |
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| SEL[1:0] = ‘00’. 24MHz |
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| SEL[1:0] = ‘01’. RESERVED |
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| SEL[1:0] = ‘10’. RESERVED |
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| SEL[1:0] = ‘11’. RESERVED |
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| ANALOG POWER | |
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1.8V PLL Power | VDD18PLL |
| 1.8V Output from the internal 1.8V PLL regulator |
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3.3V PLL Power | VDD33PLL |
| 3.3V Input to the internal 1.8V PLL regulator. |
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SMSC USB2601/USB2602 | 19 | Revision 1.6 |
| DATASHEET |
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