USB 2.0 Flash Drive Controller
Datasheet
Chapter 5 Block Diagram
Auto address generators
EP0TX_BC
EP0RX_BC
EP1TX_BC
EP1RX_BC
RAMW R_A/B
Address
Address
Address
Address
Address
Address MUX
Address
Latch phase 0, 2
SIE
512 Bytes EP2 TX/RX Buffer B |
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512 Bytes EP2 TX/RX Buffer A |
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| 64 Bytes EP1RX |
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| 64 Bytes EP1TX |
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| 64 Bytes EP0RX |
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| Flash Media |
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| M em ory | |||
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| 64 Bytes EP0TX |
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| Controller (FMC) |
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32 Bit | a | 60MHz |
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B |
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| CS[7:0] |
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| SM/ |
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| NAND Flash |
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| Latch phase 3 |
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| Latch phase 1 |
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| 8051 |
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| FM C |
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| Flash |
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| Controller |
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RAMRD_A/BAddress
Clocked byPhase 0, 2 Clock
| SIE |
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| ( Serial Interface Engine ) |
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| USB 2.0 PHY |
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| XTAL |
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| CLOCKOUT |
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| Data @ 32 bit | DMA |
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| 15Mhz | Unit |
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| NAND Flash | |
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| Data busses |
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| NAND Flash | |||
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| NAND Flash | |||
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| NAND Flash | ||||
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| XDATA |
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| 12K Byte |
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| Scratchpad |
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| SRAM |
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| GPIO |
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| 7 pins |
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| Scratchpad |
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| Interrupt Controller |
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| SRAM (768 Byte) |
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| MEM/IO Bus |
| 29pins |
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| Program Mem ory/ IO | |||||||||||
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| FAST 8051 |
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| CPU CORE |
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| Clocked by Phase 3 Clock |
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SMSC USB97C242 | Page 11 | Revision 1.4 |
DATASHEET