USB 2.0 Flash Drive Controller
Datasheet
USB97C242 Revision History
PAGE(S) | SECTION/FIGURE/ENTRY | CORRECTION | DATE REVISED |
1 | Cover | Added | Rev. 1.4 |
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5 | Chapter 1 – General Description | First bullet modified under the | Rev. 1.3 |
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| following section: | |
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| Internal program code provides the |
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| following features: |
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| Support for 1 to 8, 128Mb through |
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| 2Gb, 512byte and 2048 byte page |
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| size, 8bit parallel NAND flash |
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| memories, including multiple |
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| memory aggregates in |
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| modules (MCM) up to 8, 2Gb |
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| devices (ie 16Gb), as long as |
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| individual memory device Chip |
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| Enables are pinned out in the |
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| MCM. |
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16 | Table 7.1 - DC Electrical Characteristics | Updated High Input Leakage units. | Rev. 1.2 |
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5 | Chapter 1 - General Description | Revised list of object code software | Rev. 1.1 |
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| and licenses; internal program code | |
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| features |
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8 | Chapter 3 - Pin TablesTable 3.1 – | Updated tables | Rev. 1.1 |
| USB97C242 100 Pin Package |
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10 | Figure 4.1 – 100 Pin TQFP | Diagram updated, new pin names | Rev. 1.1 |
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12 | Table 6.1 – USB97C242 Pin | Updated misc pin section | Rev. 1.1 |
| Descriptions |
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22 | Table 11.1 - GPIO Usage | Updated table | Rev. 1.1 |
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23 | Chapter 12 - Typical Application | Typical application diagram deleted | Rev. 1.1 |
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SMSC USB97C242 | Page 3 | Revision 1.4 |
DATASHEET