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| USB 2.0 Flash Drive Controller | |
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| Datasheet | |
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| BUFFER |
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| NAME |
| SYMBOL | TYPE | DESCRIPTION |
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| MISC |
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| Crystal |
| XTAL1/ | ICLKx | 12Mhz Crystal or external clock input. |
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| Input/Extern |
| CLKIN |
| This pin can be connected to one terminal of the crystal or can be |
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| al Clock |
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| connected to an external 12Mhz clock when a crystal is not used. |
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| Input |
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| Crystal |
| XTAL2 | OCLKx | 12Mhz Crystal |
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| Output |
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| This is the other terminal of the crystal, or left open when an external |
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| clock source is used to drive XTAL1/CLKIN. It may not be used to drive |
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| any external circuitry other than the crystal circuit. |
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| Internal |
| ROMEN | IPU | When tied low, an external program memory should be connected to the |
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| ROMEN |
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| memory/data bus. The USB97C242 uses this external bus for program |
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| execution. |
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| When this pin is left unconnected or tied high, the USB97C242 uses the |
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| internal ROM for program execution. |
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| The state of this pin is latched internally on the rising edge of nRESET to |
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| determine if internal or external program memory is used. |
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| The state latched is stored in ROMEN bit of GPIO_IN1 register. |
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| General |
| GPIO1 | I/O8 | This pin may be used either as input, edge sensitive interrupt input, or |
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| Purpose I/O |
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| output. See Chapter 11 for usage by program in internal ROM. |
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| General |
| GPIO2 | I/OPU8 | This pin may be used either as input, edge sensitive interrupt input, or |
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| Purpose I/O |
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| output. See Chapter 11 for usage by program in internal ROM. |
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| General |
| GPIO3 | I/O8 | This pin may be used either as input, edge sensitive interrupt input, or |
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| Purpose I/O |
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| output. See Chapter 11 for usage by program in internal ROM. |
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| General |
| GPIO[7:4] | I/O8 | These pins may be used either as input, edge sensitive interrupt input, or |
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| Purpose I/O |
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| output. See Chapter 11 for usage by program in internal ROM. |
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| NAND flash |
| nCS[7:0] | OPU8 | These pins can be used to chip enable the NAND flash devices, when |
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| Chip Select |
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| multiple NAND flash devices are used. |
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| Signal |
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| RESET |
| nRESET | IS | This active low signal is used by the system to reset the chip. The active |
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| input |
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| low pulse should be at least 100ns wide. |
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| TEST Input |
| nTEST[0:1] | I | These signals are used for testing the chip. User should normally leave |
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| them unconnected. |
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| POWER, GROUNDS, AND NO CONNECTS |
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| VDD |
| +2.5V Core power |
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| VDDIO |
| +3.3V I/O power |
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| VDDP |
| +2.5 Analog power |
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| VSSP |
| Analog Ground Reference |
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| VDDA |
| +3.3V Analog power |
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| VSSA |
| Analog Ground Reference |
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| GND |
| Ground Reference |
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SMSC USB97C242 |
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| Page 14 | Revision 1.4 | |||
DATASHEET