SRS Labs Lock-In Amplifier, SR530 manual Analog Output and Control, A/Ds, D/As, Expand, Front Panel

U419. Analog switch U418 selects the time constant and gain. The full scale output of U418 is 5 volts.

The quadrature demodulator and low pass amplifiers are identical to that described above. The quadrature detector output is provided by U1119.

Analog Output and Control

The dc output of the demodulator/low pass amplifiers is passed to the reference input of multiplying DAC U502. The DAC is programmed with the appropriate attenuation to calibrate the overall gain of the lock-in. Every gain setting in each dynamic reserve is calibrated independently and the proper attenuations are stored in the unit's ROM.

The quadrature output is calibrated by DAC U1201. Amplifiers U1204 and U1205 buffer the two demodulator outputs to drive the X and Y BNC's.

A/D's

Analog multiplexer U504 selects the signal to be digitized by the microprocessor. This signal can be either the lock-in's in-phase or quadrature output or one of the four independent analog inputs buffered by U501. These general purpose inputs are located on the rear panel of the instrument. The selected signal is sampled and held on capacitor C502 and buffered by 4/4 U508. The A/D conversion is done by successive approximation using comparator

U514 to compare the sampled and held signal with known outputs of U505, a 12 bit DAC with a precision reference. Note that the output of U506, an 8 bit DAC is summed with the output of U505. This 8 bit DAC corrects for offset errors which can accumulate as analog voltages pass through buffers, S/H amps, and comparators. These offsets are measured after each unit is manufactured, and values to compensate for these offsets are placed in the unit's ROM. The polarity of the offset-corrected 12 bit DAC is set by 2/4 U511 and the SIGN bit yielding 13 bits of resolution from -10.24 to +10.24 volts.

D/A's

In addition to providing reference voltages for A/D conversion, the DAC output voltage may be multiplexed by U507 to one of eight sample and hold amplifiers which provide analog output and control voltages. The microprocessor refreshes each S/H amplifier every few milliseconds to prevent droop. Two of these outputs are available as general programmable outputs on the rear panel. Two are

used to program the band pass filter and the reference oscillator phase shift. One output is subtracted from the lock-in output in U508 to provide a variable offset and another is the rms noise output. The remaining two outputs generate the magnitude and phase output voltages.

Expand

3/4 U511 and 4/4 U1202 are the expand amplifiers. They provide a selectable gain of 10 to the channel 1 and 2 outputs just before the output buffers.

Front Panel

There are 71 led's on the front panel controlled by 9 serial-in, parallel-out shift registers. 8 of the shift registers are written to simultaneously and the 9th is written separately. 8 consecutive write operations are required to set the LED's in each case. The liquid crystal displays are managed by the display controllers, U6101, U6102, and U6103. Exclusive-or gates U6104, U6105 and U6106 drive the left over segments. Latches U6107 and U6108 provide the logic bits for these extra segments as well as the keyboard row strobes. U6109 reads the switch closures as the rows are scanned.

Microprocessor Control

The microprocessor, U701, is a Z80A CPU clocked at 4 MHz. 16K bytes of firmware are stored in the ROM, U702. U703 is a 2K byte static RAM, backed-up by a lithium battery. A power-down standby circuit, Q701, preserves the RAM contents when the power is turned off. The battery has a life of 5-10 years. The CPU has power-up and power-down resets to prevent erroneous execution during turn-on or short sags in the line voltage.

U704 is a 3-channel counter. One channel generates the baud rate for the RS232 interface while the other two are used to measure the frequency or period of the reference oscillator. U709 provides a gate pulse to counter 0. Multiplexer U708 selects whether the gate is a single period of the reference (period measurement) or a gate of known duration (frequency measurement). Counter 1 is a programmable divide by N counter whose output is either counted for one period of the reference,

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