SUPER MICRO Computer X8ST3-F, X8STE 2-26, T-SGPIO 0/1 & 3-SGPIO 0/1 Headers, Alarm Reset

Models: X8STE X8ST3-F

1 103
Download 103 pages 24.8 Kb
Page 50
Image 50
T-SGPIO 0/1 & 3-SGPIO 0/1 Headers

pin definitions. Refer to the board layoutAlarm ResetA.T-SPGIO 0D.3-SPGIO 1 (X8ST3-F only)2-26Manual backgroundX8ST3-F/X8STE User's Manual

T-SGPIO 0/1 & 3-SGPIO 0/1 Headers

Two T-SGPIO (Serial-Link General

Serial_Link-SGPIO

Pin Definitions

Purpose Input/Output) headers are located next to the I-SATA Port 1 on the motherboard. Additionally, two 3-SGPIO ports are also located next to SAS Port

3 on the X8ST3-F motherboard. These

Pin#

 

Definition

1

 

NC

 

3

 

Ground

 

 

 

 

5Load

7Clock

Pin Definition

2 NC

4 DATA Out

6Ground

8NC

headers are used to communicate with

the enclosure management chip in the

system. See the table on the right for

pin definitions. Refer to the board layout

below for the locations of the headers.

Alarm Reset

If three power supplies are installed and Alarm Reset (JP5) is enabled, the system will notify you when any of the three power modules fail. Connect JP5 to a micro-switch to enable you to turn off the alarm that is activated when a power module fails. See the table on the right for pin definitions.

NC: No Connections

Alarm Reset

Pin Definitions

 

 

Pin Setting

Definition

 

 

Pin 1

 

Ground

 

 

 

Pin 2

 

+5V

 

 

 

 

KB/MOUSE

USB 0/1

IPMI LAN

COM1

 

JPUSB1 JPW2

SMBUS_PS1

JPW1

FAN1

 

DIMM3A

 

 

 

DIMM3B

 

CPU FAN

 

 

 

 

DIMM2A

 

 

 

DIMM2B

 

 

LAN CTRL

DIMM1A

 

 

for IPMIl LAN

 

 

DIMM1B

A.T-SPGIO 0

B.T-SPGIO 1

C.3-SPGIO 0 (X8ST3-F only)

VGA

LAN

CTRL1

 

LAN1

 

LAN2

 

LAN

 

CTRL2

 

FAN5

Intel Processor

Slot6 PCI-E 2.0 X8 on X16

Intel X58-Express

North Bridge

Battery

SPKR1

JBT1Manual background

JWOL Manual backgroundManual backgroundManual backgroundManual backgroundManual background

 

 

JLED

 

 

 

LE1

 

 

 

 

JF1

 

 

 

 

 

1

 

 

JOH

 

 

JWD

 

FAN2

 

 

A

 

JD1

 

JAR

E

T-SGPIO1

 

 

 

SATA1-I

 

SATA0-I

 

 

 

B

D.3-SPGIO 1 (X8ST3-F only)

E.Alarm Reset

X8ST3-F/X8STE

SI/O

 

COM2

 

1

Slot5 PCI-E 2.0 X8

I-Button

Slot4 PCI-E 2.0 X4 on X8

BMC

Firmware

JPL1

 

 

 

JPL2

 

JPG1

 

Slot3 PCI-E 2.0 X8

 

 

 

 

BMC CTRL

Slot2 PCI 33MHz

 

WPCM 450

 

JBMC1

 

SAS0

Slot1 PCI 33MHz

 

JPUSB3

 

 

Floppy

JI2C1

JI2C2

 

BMC JTAG

USB2 USB3

 

 

 

 

 

BIOS

 

Intel ICH10R

 

 

 

South Bridge

 

 

 

SAS CTRL

 

 

3-SGPIO1

CLSI 1068E

SAS1

SAS2

SAS3

SAS4

SAS5 LES2 SAS6

 

 

3-SGPIO2

D

 

JPS2

T-SGPIO2 I-SATA3

I-SATA2

 

I-SATA5

I-SATA4

 

USB 6/7

 

USB 4/5

JPUSB2

 

JPS1

JL1

 

1

LES1Manual background FAN3Manual backgroundManual backgroundManual backgroundManual backgroundManual backgroundManual background

Manual backgroundSAS7Manual backgroundManual background

FAN4

2-26

Page 50
Image 50
SUPER MICRO Computer X8ST3-F, X8STE user manual 2-26, T-SGPIO 0/1 & 3-SGPIO 0/1 Headers, Alarm Reset