SUPER MICRO Computer X7DBT-INF, XDGT, X7DGT-INF Following are for boot block in Flash ROM

	Appendix B: BIOS POST Codes
POST Code	Description
D2h	Unknown interrupt
D4h	Check Intel Branding string
D8h	Alert Standard Format initialization
D9h	Late init for IPMI
DEh	Log error if micro-code not updated properly
The following are for boot block in Flash ROM
POST Code	Description
E0h	Initialize the chipset
E1h	Initialize the bridge
E2h	Initialize the CPU
E3h	Initialize system timer
E4h	Initialize system I/O
E5h	Check force recovery boot
E6h	Checksum BIOS ROM
E7h	Go to BIOS
E8h	Set Huge Segment
E9h	Initialize Multi Processor
EAh	Initialize OEM special code
EBh	Initialize PIC and DMA
ECh	Initialize Memory type
EDh	Initialize Memory size
EEh	Shadow Boot Block
EFh	System memory test
F0h	Initialize interrupt vectors
F1h	Initialize Run Time Clock
F2h	Initialize video
F3h	Initialize System Management Manager
F4h	Output one beep
F5h	Clear Huge Segment
F6h	Boot to Mini DOS
F7h	Boot to Full DOS

*If the BIOS detects errors on 2C, 2E, or 30 (base 512K RAM error), it displays an additional word-bitmap (xxxx) indicating the address line or bits that have failed. For example, “2C 0002” means address line 1 (bit one set) has failed. “2E 1020" means data bits 12 and 5 (bits 12 and 5 set) have failed in the lower 16 bits. The BIOS also sends the bitmap to the port-80 LED display. It fi rst displays the checkpoint code, followed by a delay, the high-order byte, another delay, and then the loworder byte of the error. It repeats this sequence continuously.

B-5