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42 | MUTER | O | Line muting on/off control signal output terminal (for | “H”: muting on | |
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43 | XVDD | — | Power supply terminal (+5V) (crystal oscillator system) |
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44 | XOUT | O | System clock output terminal (16.9344 MHz) |
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45 | XIN | I | System clock input terminal (16.9344 MHz) |
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46 | XVSS | — | Ground terminal (crystal oscillator system) |
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47 | SBSY | O | C1, C2, single correction, and double correction monitor output to the CD text decoder (IC104) | ||
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48 | EFLG | O | Subcode P to W output terminal |
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49 | PW | O | Subcode frame sync signal output to the CD text decoder (IC104) |
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50 | SFSY | O | Write frame clock signal output to the CD text decoder (IC104) |
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51 | SBCK | I | Subcode reading clock signal input from the CD text decoder (IC104) (schmitt input) | ||
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52 | FSX | O | 7.35 kHz sync signal output divided from the crystal oscillation |
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53 | WRQ | O | Subcode Q synchronizing signal output to the system controller (IC501) | ||
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54 | RWC | I | Command chip enable signal input from the system controller (IC501) (schmitt input) | ||
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55 | SQOUT | O | Subcode Q data output to the system controller (IC501) |
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56 | COIN | I | Command serial data input from the system controller (IC501) |
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57 | CQCK | I | Command serial clock signal input from the system controller (IC501) (schmitt input) | ||
Fetching clock input or subcode extracting clock input from SQOUT (pin %∞) | |||||
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58 | RES | I | System reset signal input from the reset signal generator (IC201) | “L”: reset | |
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H” | |||||
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59 | TEST11 | O | Test output terminal Not used (open) |
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60 | 16M | O | Master clock signal (16.9344 MHz) output to the CD text decoder (IC104) | ||
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61 | 4.2M | O | Reference clock signal (4.2336 MHz) output to the RF amplifier (IC102) | ||
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62 | TEST5 | I | Test input terminal (fixed at “L” in this set) |
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63 | CS | I | Chip select signal input terminal Not used (fixed at “L”) |
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64 | TEST1 | I | Test input terminal (fixed at “L” in this set) |
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