Texas Instruments ADS5525, 46, 27 THS4509 + ADS5545 EVM Performance Clock Input, Digital Outputs

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Circuit Description

The schematics present various interface options between the amplifier and the ADC. Depending on the input frequencies of interest, further performance optimization can be had by designing a corresponding filter. In its default configuration, R43, R44, and C119 form a first-order, low-pass filter with a cutoff frequency of 70 MHz. Figure 2 shows the performance of the ADS5545 using the THS4509 path.

Amplitude − dBFS

10
		1
0
−10
−20
−30
−40
−50
−60
−70
−80						3				5				x
−90								4
−100
				2
−110
−120
−130
−135
0	5	10	15	20	25	30	35	40	45	50	55	60	65	70	75	80	85

f − Frequency − MHz

G002

Figure 2. THS4509 + ADS5545 EVM Performance

3.2.4Clock Input

A single-ended, harmonically filtered, low-phase-noise, 1.5-Vrms sinusoidal input should be applied to J7. The frequency must not exceed the device specification. In the EVM default configuration, both SPJ1 and SJP2 must have pins 1 and 2 shorted.

In the board default configuration, the transformer provides single-ended to differential conversion. The transformer has an impedance ratio of 4.

3.2.5Digital Outputs

For compatibility with a broad range of logic analyzers, the EVM outputs 3.3-V parallel CMOS data on header J4, independent of the ADC operational mode. The Xilinx™Spartan™-3E FPGA provides the necessary translation, and it configures itself using one of two different logic files stored in the PROM, based on the EVM configuration. The CMOS data output of the FPGA is contained in data header J4 and is a standard 40-pin header on a 100-mil grid, which allows easy connection to a logic analyzer. The connector pinout is listed in Table 3. For quick setup, the eye diagram is shown in Figure 3. No setup or hold-time adjustments must be made to the logic analyzer if using the rising edge of the output clock to latch in the data.

Note: The eye diagram shown is the output of the FPGA at 210 MSPS, not that of the ADC. For the ADC output timing, see the respective device data sheet.

SLWU028B –January 2006 –Revised November 2006 9

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