CDCM7005 Functional Block Diagram
1.1 CDCM7005 Functional Block Diagram
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| VCC | AVCC |
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| Selected REF Signal |
|
REF_SEL | Manual & |
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Automatic | freq. detect | ||
| CLK Select | > 2 MHz | |
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| freq. detect |
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| > 2 MHz |
PRI_REF |
| MUXREF |
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| LVCMOS | Progr. Delay | |
| Reference | M | |
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| ||
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| |
SEC_REF |
| Clock |
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| |
| Feedback | Progr. Delay |
| Clock | N |
CTRL_LE | SPI LOGIC |
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CTRL_DATA |
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|
CTRL_CLK |
| PECL |
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| |
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| to |
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| LVCMOS |
PD |
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RESET or |
| FB_MUX |
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| |
HOLD |
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|
VCC_CP
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| STATUS_REF / | |
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| PRI_SEC_CLK | |
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| STATUS_VCXO | |
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| / I_REF_CP | |
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| PLL_LOCK | |
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| LOCK | HOLD |
| |
Progr. Divider |
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| ||
M | 210 |
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| |
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| PFD | Charge | CP_OUT | |
Progr. Divider | Pump | ||||
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| ||||
N | 212 |
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| |
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| Current | |
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| Reference | |
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| LV | |
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| CMOS | |
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| Y0 MUX |
| Y0A | |
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| LV | ||
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| PECL | ||
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| Y0B | ||
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| ||
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| LV | |
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|
| CMOS | |
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| LV | |
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| CMOS | |
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| Y1A | |
VCXO_IN 
PECL
VCXO_IN 
INPUT
⎟ 1
⎟ 2
⎟ 3
⎟ 4 
⎟ 6
⎟/8
⎟ 16 | |
⎟ 4o90 | |
⎟ 8 | 90o |
| |
P16−Div | |
P Divider
Y1MUX | LV | |
PECL | ||
Y1B | ||
| ||
| LV | |
| CMOS | |
| LV | |
| CMOS | |
Y2 MUX | Y2A | |
LV | ||
PECL | ||
Y2B | ||
| ||
| LV | |
| CMOS | |
| LV | |
| CMOS | |
Y3 MUX | Y3A | |
LV | ||
PECL | ||
Y3B | ||
| ||
| LV | |
| CMOS |
VBB | Bias Generator | |
VCC − 1.3 V | ||
|
| LV | |
| CMOS | |
Y4 MUX | Y4A | |
LV | ||
PECL | ||
Y4B | ||
| ||
| LV | |
| CMOS |
GND
