Application Circuit Diagram
5.1 Application Circuit Diagram
The following applications sections the two loop filter configurations are discussed.
5.1.1Passive Loop Filter
The passive loop filter is a second order filter (two poles, one zero). The zero is required for the overall loop stability. R1, C1, and C2 generate the dominant pole of the system. A second pole is introduced by R2 and C3.
Figure 5−1. CDCM7005 With a Passive Loop Filter Configuration
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| VC(X)O |
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| R2 | ||
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| 491.52 MHz |
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| 160 Ω | |||
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| PECL_OUT_B |
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| V_CTRL |
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| PECL_OUT |
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| C3 |
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| 100 nF |
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| CDCM7005 |
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| PRI_REF |
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| SEC_REF |
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| R1 |
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| 4.7 kΩ |
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| C2 |
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| CP_OUT |
| 100 nF |
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| CTRL_LE |
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| C1 | |
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| 22 µF | |
SPI |
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| CTRL_DATA |
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| STATUS_REF |
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| VCC | CTRL_CLK |
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VCC |
| STATUS_VC(X)O |
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| PLL_LOCK |
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| 130 Ω |
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| 10 nF | |
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| YnA |
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130 Ω |
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| VC(X)O_IN |
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| 10 nF | ||
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| VC(X)O_IN_B | YnB |
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R | Ω | R | Ω |
| R | R | Ω |
82 | 82 |
| 150 Ω | 150 | |||
