Texas Instruments SLOU061A

EVM Board Layout

2-9

Evaluation Module Layout

2.7 EVM Board Layout

Figures 2–6 and 2–7 show the EVM top and bottom board layouts,

respectively.

Figure 2–6.EVM Board Layout—To p

Contents

Main Page Preface Related Documentation From Texas Instruments FCC Warning Trademarks Page Contents Figures Table Introduction 1.1 Design Features 1.2 Power Requirements Chapter 2 Evaluation Module Layout Topic Page 2.1 Physical Considerations 2.2 Area 100Single Device SOIC Figure 21.Area 100 SchematicSingle Device, SOIC (8 pin) Physical Considerations 2-4 Evaluation Module Layout 2.3 Area 200Dual Device SOIC Figure 22.Area 200 SchematicDual Device, SOIC (14 pin) 2.4 Area 300Quad Device SOIC Physical Considerations 2-6 Evaluation Module Layout Figure 23.Area 300 SchematicQuad Device SOIC (16 pin) 2.5 General Power Dissipation Considerations Figure 24.Maximum Power Dissipation vs Free-Air Temperature Table 21.Dissipation Rating Table Page Page Page Chapter 3 Example Circuits Topic Page Schematic Conventions 3-2 Example Circuits 3.1 Schematic Conventions 3.2 Inverting Amplifier Figure 31.Inverting Amplifier With Dual Supply Using Area 100 Noninverting Amplifier () 6 100 k 3 + () Figure 33.Single Operational Amplifier Differential Amplifier With Single Supply Using Area 100 Sallen-Key Low-Pass Filter 3-5 3.5 Sallen-Key Low-Pass Filter Qf 1 1f f 2j f Where: fo1 2mnRC And Qmn m 1 3.6 Sallen-Key High-Pass Filter Sallen-Key High-Pass Filter 3-7 Figure 35.Sallen-Key High-Pass Filter With Single Supply Using Area 200 3.7 Two Operational Amplifier Instrumentation Amplifier Two Operational Amplifier Instrumentation Amplifier 3-9 Figure 36.Two Operational Amplifier Instrumentation Amplifier Wwith Single Supply Using Area 200 3.8 Quad Operational Amplifier Instrumentation Amplifier Quad Operational Amplifier Instrumentation Amplifier 3-11 Figure 37.Quad Operational Amplifier Instrumentation Amplifier With Dual Supply Using Area 300