4.6 Clocks Tab
4.6.1 Configuring the Codec Clocks and Fsref Calculation
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TLV320AIC3007EVM Software
Figure 9. Clocks Tab
The TLV320AIC3007 provides a phase-locked loop (PLL) that allows flexibility in the clock generation forthe ADC and DAC sample rates. The Clocks tab contains the controls that can be used to configure theTLV320AIC3007 for operation with a wide range of master clocks. See the Audio Clock GenerationProcessing figure in the TLV320AIC3007 data sheet for further details of selecting the correct clocksettings.
For use with the PC software and the USB-MODEVM, the clock settings must be set a certain way. If thesettings are changed from the default settings which allow operation from the USB-MODEVM clockreference, the EVM settings can be restored automatically by clicking the Load EVM USB Settingsbutton. Note that changing any of the clock settings from the values loaded when this button is pushedcan result in the EVM not working properly with the PC software or USB interface. If an external audio busis used (audio not driven over the USB bus), then settings can be changed to any valid combination. SeeFigure 9 .
The codec clock source is chosen by the CODEC_CLK Source control. When this control is set toCLKDIV_OUT, the PLL is not used; when set to PLLDIV_OUT, the PLL is used to generate the clocks.
Note: Per the TLV320AIC3007 data sheet, the codec must be configured to allow the value ofFsref to fall between the values of 39 kHz to 53 kHz.
SLAU286 – June 2009 TLV320AIC3007EVM-K 15Submit Documentation Feedback