Appendix C – XP-15 Hardware Control and Status Registers
The
The following tables describe the
As defined by the PCI Local Bus Specification Rev. 2.2, the
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| Register Name |
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| Offset | Type | Size |
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| 0 |
| 0h | R/W | 32 bits |
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| Low PCI SN command address register[31..0] | 0 |
| 4h | R/W | 32 bits |
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| High PCI SN command address register[63..32] | 0 |
| 8h | R/W | 32 bits |
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| Low PCI SN response address register[31..0] | 0 |
| Ch | R/W | 32 bits |
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| High PCI SN response address register[63..32] | 0 |
| 10h | R/W | 32 bits |
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| Bit # |
| Name | Type |
| Description |
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| RESERVED | N/A |
| These bits are reserved. |
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| 15 |
| Reset | WO |
| Softreset, puts the |
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| 14 |
| Start | WO |
| Informs |
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| 13 |
| END | WO |
| Indicates host is big Endian. |
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| RESERVED | N/A |
| These bits are reserved. |
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| 9 |
| 64 | WO |
| Indicates |
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| 8 |
| RESERVED | N/A |
| This bit is reserved. |
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| 7 |
| DMADONE | RO |
| Indicates the DMA is finished. |
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| 6 |
| STOP | RO |
| Indicates the STOP bit has been encountered. |
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| 5 |
| PAUSE | RO |
| Indicates the |
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| 4 |
| ERR | RO |
| Indicates the |
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PCI200 User Guide |
| Texas Memory Systems, Inc. (8/6/01) |
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