Toshiba SR-C8002 15/24

15/24 SR-C8002 Rev.1.0

6.2.3.Timing of Host Interface (DMA Multi)

Figure 10 shows the Host Interface DMA multi word Timings

DMARQ

DMACK-*1

DIOR-/DIOW-*1

Read

DD0-15

Write

DD0-15

tI tJ

*1: In all timing diagrams, the low line indicator negated, and the upper line

indicators asserted.

Multi word DMA

timing parameters min(ns) max(ns) Min time (ns) Max time (ns)

t0 Cycle time 120

tC DMACK to DMREQ delay ---

tD DIOR-/DIOW-16-bit 70

tE DIOR- data access ---

tF DIOR- data hold 5

tZ DMACK- to tristate 25

tG DIOR/DIOW- data setup 20

tH DIOW- data hold 10

tI DMACK to DIOR-/DIOW- setup 0

tJ DIOR-/DIOW- to DMACK hold 5

tKr DIOR- negated pulse width 25

tKw DIOW- negated pulse width 25

tLr DIOR- to DMREQ delay 35

tLw DIOR- to DMREQ delay 35

Figure 10 Host Interface Timing (Multi Word DMA Mode 2)

Contents

Main TOSHIBA LIMITATION OF LIABILITY Warnings: Notice Contents Page 1/24 2/24 3/24 4/24 5/24 6/24 7/24 Page 9/24 10/24 TC94A03 Figure 4 Configuration BH6526FV RC5E839 11/24 12/24 13/24 Figure 8 Signal Specifications 14/24 6.2.2.Timing of Host Interface (PIO) Figure 9 shows the Host Interface Timings Figure 9 Host Interface Timing (PIO Mode4) *1: In all timing diagrams, the low line indicator negated, and the upper line indicators asserted. 15/24 6.2.3.Timing of Host Interface (DMA Multi) Figure 10 shows the Host Interface DMA multi word Timings Figure 10 Host Interface Timing (Multi Word DMA Mode 2) *1: In all timing diagrams, the low line indicator negated, and the upper line indicators asserted. 16/24 Figure 11 Connector pin assignments 17/24 6.4. Support Command List ATAPI Packet Command 18/24 - 19/24 20/24 21/24 22/24 23/24 TOSHIBA EU-Declaration of Conformity Annex 1 24/24 EU-Declaration of Conformity CD-R/RW Drive SR-C8002 X Manufactuer(s) Location Address