Tyan Computer N3600QX warranty Feature Option Description NorthBridge Chipset Configuration

Feature	Option	Description
NorthBridge Chipset	Configuration
		This controls the timing delay (in clock
CAS Latency (Tcl)	Read only	cycles) before SDRAM starts a read
		command after receiving it.
		When DRAM is refreshed, both rows
		and columns are addressed
		separately. This setup item allows you
RAS/CAS Delay (Trcd)	Read only	to determine the timing of the transition
		from RAS (row address strobe) to CAS
		(column address strobe). The less the
		clock cycles, the faster the DRAM
		performance.
		This setting allows you to select the
		number of clock cycles allotted for the
Min Active RAS (Tras)	Read only	RAS pulse width, according to DRAM
		specifications. The less the clock
		cycles, the faster the DRAM
		performance.
		This item controls the number of cycles
		for Row Address Strobe (RAS) to be
		allowed to precharge. If insufficient
Row Precharge Time	Read only	time is allowed for the RAS to
		accumulate its chage before DRAM
(Trp)
		refresh, refresh may be incomplete and
		DRAM may fail to retain data. This
		item applies only when synchronous
		DRAM is installed in the system.
		Auto uses hardware compensation
	Read only	values. Other values add to or subtract
RAS/RAS Delay (Trrd)		from hardware generated value.
		Recommended setting is Auto.
Row Cycle (Trc)	Read only	Bits 7-4. RAS#-active to RAS#-active
		or auto refresh of the same bank.
		Bits 3-0. This filed should be loaded
Asynchronous Latency	Read only	with a 4-bit value equal to the
		maximum asynchronous latency in the
		DRAM read round-trip loop.

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