BIOS Setup
DRAM CAS Latency
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends on the DRAM timing. The settings are: 1.5, 2, 2.5, 3.
Bank Interleave
This field selects
Precharge To Active (Trp)
This item controls the number of cycles for Row Address Strobe (RAS) to be allowed to precharge. If insufficient time is allowed for the RAS to accumulate its charge before DRAM refresh, refreshing may be incomplete and DRAM may fail to retain data. This item applies only when synchronous DRAM is installed in the system. Available settings: 2T, 3T.
Trans Non-DDR400/DDR400
This controls the timing delay (in clock cycles) before
Active to CMD (Trcd)
When DRAM is refreshed, both rows and columns are addressed separately. This setup item allows you to determine the timing of the transition from RAS (row address strobe) to CAS (column address strobe). The less the clock cycles, the faster the DRAM performance. Setting options: 2T, 3T.
DRAM Burst Length
This setting allows you to set the size of
DRAM Command Rate
This setting controls the SDRAM command rate. Selecting 1T allows SDRAM signal controller to run at 1T (T=clock cycles) rate. Selecting 2T makes SDRAM signal controller run at 2T rate. 1T is faster than 2T. Setting options: 1T Command, 2T Command.
DDR Voltage
Adjusting the DDR voltage can increase the DDR speed. Any changes made to this setting may cause a stability issue, so changing the DDR voltage for