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3.2Pin Descriptions
The Hirose DF12C
The table below defines the pin functions. Note that this
Pin Signal
No.
1Analogue 0
3 Analogue 1
5SPI_MISO
7SPI_CSB
9 SPI_CLK
11 GND
13 RESET
15 GND
17 SPI_MOSI
19 UART_CTS
21 UART_TX
23 UART_RTS
25 UART_RX
27 VCC_3V3
29 VCC_5V
31 N/C
33 GPIO6 **
35 GPIO7 **
37 GPIO8 **
39 GPIO9
Notes:
Description
1.8v Max
1.8v Max
SPI bus serial O/P
SPI bus chip select I/P
SPI bus clock I/P
Reset I/P *
SPI bus serial I/P
Clear to Send I/P
Transmit Data O/P
Request to Send O/P
Receive Data I/P
3.3V Monitor
3.6V < VIN < 7.0V
I/O for Host
I/O for Host
I/O for Host
I/O for Host
Pin | Signal | Description |
No. |
|
|
|
|
|
2 | GPIO1 | I/O for Host. |
|
|
|
4 | GPIO2 | I/O for Host |
|
|
|
6 | UART_RI | ‘Ring’ Input or Output |
|
|
|
8 | UART_DCD | Input or Output |
|
|
|
10 | UART_DSR | Input |
|
|
|
12 | GPIO3/UART_DTR | I/O for Host |
|
|
|
14 | GPIO4 | I/O for Host & LED |
|
|
|
16 | GPIO5 | I/O for Host |
|
|
|
18 | GND |
|
|
|
|
20 | PCM_CLK | PCM Clock I/P |
|
|
|
22 | PCM_IN | PCM Data I/P |
|
|
|
24 | PCM_SYNC | PCM Sync I/P |
|
|
|
26 | PCM_OUT | PCM Data O/P |
|
|
|
28N/C
30GND
32 | USB / RESERVED | Do not connect |
|
|
|
34 | USB / RESERVED | Do not connect |
|
|
|
36GND
38GND
40N/C
*The reset circuitry within the BISM Serial Modules now incorporates a
**Pins 33, 35 and 37 were N/C on BISM1. Pin 39 was a 1V8 monitor. Designers migrating between designs should be aware that these are now available as I/O. Default configuration is as an input
PIO lines can be configured through software to be either inputs or outputs with weak or strong pull- ups or
UART_RX, UART_TX, UART_CTS, UART_RTS, UART_RI, UART_DCD and UART_DSR are all 3.3v level logic. For example, when RX and TX are idle they will be sitting at 3.3V. Conversely for handshaking pins CTS, RTS, RI, DCD, DSR a 0v is treated as an assertion.
Pin 6 (UART_RI) is active low. It is normally 3.3v. When a remote device initiates a connection, this pin goes low. This means that when this pin is converted to RS232 voltage levels it will have the correct voltage level for assertion.