IBM manual Z10 EC Performance, Large System Performance Reference, CPU Measurement Facility

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z10 EC Performance

The performance design of the z/Architecture can enable the server to support a new standard of performance for applications through expanding upon a balanced system approach. As CMOS technology has been enhanced to support not only additional processing power, but also more PUs, the entire server is modifi ed to support the increase in processing power. The I/O subsystem supports a greater amount of bandwidth than previous generations through internal changes, providing for larger and faster volume of data movement into and out of the server. Sup- port of larger amounts of data within the server required improved management of storage confi gurations, made available through integration of the operating system and hardware support of 64-bit addressing. The combined bal- anced system design allows for increases in performance across a broad spectrum of work.

Large System Performance Reference

IBM’s Large Systems Performance Reference (LSPR) method is designed to provide comprehensive z/Archi- tecture processor capacity ratios for different confi gura- tions of Central Processors (CPs) across a wide variety of system control programs and workload environments. For z10 EC, z/Architecture processor capacity identifi er is defi ned with a (7XX) notation, where XX is the number of installed CPs.

Based on using an LSPR mixed workload, the perfor- mance of the z10 EC (2097) 701 is expected to be up to 1.62 times that of the z9 EC (2094) 701.

The LSPR contains the Internal Throughput Rate Ratios (ITRRs) for the z10 EC and the previous-generation zSeries processor families based upon measurements and projections using standard IBM benchmarks in a con- trolled environment. The actual throughput that any user

may experience will vary depending upon considerations such as the amount of multiprogramming in the user’s job stream, the I/O confi guration, and the workload processed.

LSPR workloads have been updated to refl ect more closely your current and growth workloads. The classifi ca- tion Java Batch (CB-J) has been replaced with a new clas- sifi cation for Java Batch called ODE-B. The remainder of the LSPR workloads are the same as those used for the z9 EC LSPR. The typical LPAR confi guration table is used to establish single-number-metrics such as MIPS and MSUs. The z10 EC LSPR will rate all z/Architecture processors running in LPAR mode, 64-bit mode, and assumes that HiperDispatch is enabled.

For more detailed performance information, consult the Large Systems Performance Reference (LSPR) available at: http://www.ibm.com/servers/eserver/zseries/lspr/.

CPU Measurement Facility

The CPU Measurement Facility is a hardware facility which consists of counters and samples. The facility provides a means to collect run-time data for software performance tuning. The detailed architecture information for this facility can be found in the System z10 Library in Resource Link™.

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Contents IBM System z10 Enterprise Class z10 EC Reference Guide Table of Contents IBM System z10 Enterprise Class z10 EC Overview Specialty engines offer an attractive alternative Just-in-time deployment of IT resourcesNumerical computing on the chip Order of introductionLiberating your assets with System z ArchitectureEvolving for your business Z10 EC ArchitecturePage Commitment to system integrity Page Linux on System z VSETPF Operating System ESA/390 Z10 ECPage Page Z10 EC Design and Technology Z10 EC Model Z10 EC Base and Sub-capacity Offerings Z10 EC model upgradesCPU Measurement Facility Z10 EC PerformanceLarge System Performance Reference System I/O Configuration Analyzer Z10 EC I/O SubsystemZ10 EC Channels and I/O Connectivity Ficon Express4 and Ficon Express2 Performance Concurrent UpdateSupport of Spanned Channels and Logical Partitions Modes of OperationFCP increased performance for small block sizes Ficon Support for Cascaded DirectorsFCP Channels FCP Full fabric connectivity Scsi IPL now a base functionFicon and FCP for connectivity to disk, tape, and printers Platform and name server registration in Ficon channelIt will register Program Directed re-IPL NPort ID VirtualizationPort density or granularity Feature Infrastructure Ports perOSA-Express3 Ethernet features Summary of benefits OSA-Express2 availability FeaturesPurpose/Traffic TypeOSA-Express3 Gigabit Ethernet LX OSA-Express3 10 Gigabit Ethernet SROSA-Express3 Gigabit Ethernet SX Four-port exploitation on OSA-Express3 GbE SX and LXDynamic LAN idle for z/OS Network Traffic AnalyzerLayer 2 transport mode When would it be used? Link aggregation for z/VM in Layer 2 modeOSA Layer 3 Virtual MAC for z/OS Direct Memory Access DMAHardware data router IBM Communication Controller for Linux CCLOSA/SF Virtual MAC and Vlan id Display Capability OSA Integrated Console ControllerRemove L2/L3 LPAR-to-LPAR Restriction HiperSockets HiperSockets Enhancement for zIIP Exploitation CP Assist for Cryptographic Function Cpacf Security CryptographyCan Do IT securely Configurable Crypto Express2 Secure Key AES Dynamically add crypto to a logical partitionEnhancement with TKE 5.3 LIC TKE 5.3 workstation and support for Smart Card ReaderTKE additional smart cards System z10 EC cryptographic migrationImproved Key Exchange With Non-CCA Cryptographic Systems Remote Loading of Initial ATM KeysRemote Key Loading Benefits Capacity on Demand Temporary Capacity On Demand CapabilitiesAmendment for CBU Tests Capacity Provisioning System z9 System z10 OS Capacity provisioning allows you to set up rulesRAS Design Focus Reliability, Availability, and Serviceability RASEnhanced Book Availability Availability FunctionsHardware System Area HSA Concurrent Physical Memory Replacement Concurrent Physical Memory UpgradeConcurrent Defective Book Replacement Enhanced Driver MaintenancePlan Ahead Memory Transparent SparingPower Monitoring Service EnhancementsPower Estimation Tool Environmental EnhancementsIBM Systems Director Active Energy Manager Parallel Sysplex Cluster TechnologyCoupling Facility Control Code Cfcc Level Improved service time with Coupling Facility DuplexParallel Sysplex Coupling Connectivity Coupling Facility Configuration AlternativesSystem-Managed CF Structure Duplexing Coupling Connectivity for Parallel Sysplex Introducing long reach InfiniBand coupling linksZ10 EC Max Z10 Coupling Link OptionsPreview Improved STP System Management with Time synchronization and time accuracy on z10 ECServer Time Protocol STP Continuous availability of NTP servers used as Exter Enhanced Network Time Protocol NTP client supportApplication Programming Interface API to automate Enhanced STP recovery when Internal Battery FeatureNTP server on Hardware Management Console HMC Internal Battery Feature Recommendation Family Machine Type HMC System SupportInternet Protocol, Version 6 IPv6 HMC/SE Console MessengerHMC z/VM Tower systems management enhancements Gdps Implementation Services for Parallel SysplexFiber Quick Connect for Ficon LX Environments Z10 EC Dimensions Z9 EC Number of Frames 2 Frame Z10 EC Physical Characteristics Z10 EC Configuration DetailZ10 EC Environmentals Model O Cage Model O CageOSA-Express3 and OSA-Express2 Features Min Max Processor Unit Features ModelCPs IFLs ICFsGeneral Information Z9 BC Coupling Facility CF Level of SupportStatement of Direction Resource Link PublicationsFollowing Redbook publications are available now ZSO03018-USEN-02
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