IBM P5 570 manual Power chip evolution, POWER4

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POWER5 chips extensively use a fine-grained, dynamic clock-gating mechanism. This mechanism gates off clocks to a local clock buffer if dynamic power management logic knows that the set of latches that are driven by the buffer will not be used in the next cycle. This allows substantial power saving with no performance impact. In every cycle, the dynamic power management logic determines whether a local clock buffer that drives a set of latches can be clock-gated in the next cycle.

In addition to the switching power, leakage power has become a performance limiter. To reduce leakage power, the POWER5 chip uses transistors with low threshold voltage only in critical paths. The POWER5 chip also has a low-power mode, enabled when the system software instructs the hardware to execute both threads at the lowest available priority. In low power mode, instructions dispatch once every 32 cycles at most, further reducing switching power. The POWER5 chip uses this mode only when there is no ready task to run on either thread.

2.1.3 The POWER chip evolution

The p5-570 system complies with the RS/6000 platform architecture, which is an evolution of the PowerPC Common Hardware Reference Platform (CHRP) specifications. Figure 2-3shows the POWER chip evolution.

 

 

 

 

 

 

POWER4+

 

 

 

 

 

 

1.2 to 1.9 GHz

 

 

Models 270, B80, and

 

POWER4

p615, p630,

 

 

POWER3 SP Nodes

 

1.0 to 1.3

 

 

 

Power3-II

 

p650, p655, p670

 

 

 

RS64-IV

GHz

and p690

 

 

333 / 375 /

p630, p650, p655,

64bit

SP Nodes

450

600 / 750

p670, and p690

Note: Not all

 

 

RS64-III

 

 

Power3

pSeries p620, p660,

processor speeds

 

450

 

 

200+

and p680

 

available on all

 

 

 

 

models

 

 

 

F80, H80, M80, S80

 

 

 

 

 

RS64-II

 

 

 

 

 

RS64-II

340

 

 

 

 

RS64

262.5

H70

 

SOI

 

32bit

125

S7A

 

 

 

 

 

 

 

 

S70

 

 

 

 

 

604e

+ SOI =

 

332 /

 

375

Copper =

F50

 

POWER4™

0.18 microns

1.0 to

 

1.0 to

1.3 GHz

 

1.3 GHz

Core

 

Core

 

 

 

Shared L2

Distributed Switch

2001

–Distributed Switch

–Shared L2

–LPAR

–Autonomic computing

–Chip multiprocessing

POWER4+

0.13 microns

1.2 to

1.2 to

1.9GHz 1.9 GHz

Core Core

Shared L2

Distributed Switch

2002-3

–Larger L2

–More LPARs

–High-speed Switch

POWER5TM

0.13 microns

1.5 to

 

1.5 to

1.9 GHz

 

1.9 GHz

Core

 

Core

 

 

 

 

 

Shared L2

 

 

 

 

 

Mem Ctl

 

 

 

 

 

 

 

Distributed Switch

 

 

2004

–Larger L2 and L3 caches

–Micro-partitioning

–Enhanced Distributed Switch

–Enhanced core parallelism

–Improved floating-point

–performance

–Faster memory environment

Figure 2-3 The POWER chip evolution

22p5-570 Technical Overview and Introduction

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Contents IBM Eserver p5 Technical Overview Introduction Page IBM Sserver p5 570 Technical Overview Introduction First Edition July Contents Page Page Vi p5-570 Technical Overview and Introduction Vii Trademarks Preface Team that wrote this RedpaperBecome a published author Comments welcomeGeneral description P5-570 Technical Overview and Introduction System specifications Physical packageMinimum and optional features View from the frontProcessor card features Processor card FC DescriptionMemory features Disk and media features5 I/O drawers USB diskette driveModel D10 I/O drawer Model D10 I/O drawer physical package Model D11 I/O drawer Model D20 I/O drawerDrawers and usable PCI slots Model D20 I/O drawer physical packageValue Paks Hardware Management Console modelsModel type conversion System racksIBM RS/6000 7014 Model T00 Enterprise Rack IBM RS/6000 7014 Model T42 Enterprise Rack AC Power Distribution Unit and rack contentRack-mounting rules for p5-570 and I/O drawers Additional options for rack Flat panel display optionsHardware Management Console 7310 Model CR2 OEM rackIBM 7212 Model 102 TotalStorage Storage device enclosure Statement of direction 18 p5-570 Technical Overview and Introduction Architecture and technical overview POWER5 chip POWER4 POWER5Simultaneous multi-threading Dynamic power managementEnhanced SMT features ST operationPower chip evolution POWER4Processor cards CMOS, copper, and SOI technologyProcessor drawer interconnect cables Processor card with DDR1 memory socket layout viewProcessor clock rate Pmcycles -mMemory subsystem Memory placement rulesMemory restriction Memory throughput System busesRIO-2 buses and GX+ card SP bus Internal I/O subsystemPCI-X slots and adapters Scsi adapters LAN adaptersGraphic accelerators Bit and 32-bit adaptersInternal storage Internal hot swappable Scsi disksInternal media devices Internal RAID optionsHot-swap disks and Linux 1 I/O drawers External I/O subsystems2 7311 Model D10 and 7311 Model D11 I/O drawers Model D11 features Model D10 features3 7311 Model D20 I/O drawer 4 7311 I/O drawer and RIO-2 cabling Model D20 internal Scsi cabling5 7311 I/O drawer and Spcn cabling Cost Optimized Performance OptimizedExternal disk subsystems IBM 2104 Expandable Storage PlusIBM TotalStorage FAStT Storage servers IBM 7133 Serial Disk Subsystem SSAIBM TotalStorage Enterprise Storage Server Virtualization Advanced Power Virtualization featureDynamic logical partitioning Virtual Ethernet15shows the POWER5 partitioning concept Micro-Partitioning technologyPOWER5 Partitioning Virtual I/O ServerService processor Partition Load ManagerService processor base Service processor extenderBoot process IPL flow without an HMC attached to the systemHardware Management Console IPL flow with an HMC attached to the systemManaged systems Definitions of partitionsProfiles Hardware requirements for partitioning System Management ServicesSpecific partition definitions used for Micro-Partitioning Boot options 17 System Management Services main menuAdditional boot options DVD-ROM, DVD-RAMSecurity Operating system requirementsAIX 5L Linux Linux supportCapacity on Demand, RAS, and manageability Way 1.9 GHz POWER5 processor card with DDR1 memory slots Processor Capacity Upgrade on Demand methodsWay 1.65 GHz POWER5 processor card Way 1.9 GHz POWER5 processor card with DDR2 memory slotsCapacity Upgrade on Demand for memory How to report temporary activation resources Capacity Upgrade on Demand for memory feature codesFault avoidance Reliability, availability, and serviceabilityTrial Capacity on Demand Permanent monitoring First Failure Data CaptureMutual surveillance Self-healing Memory reliability, fault tolerance, and integrityEnvironmental monitoring Resource deallocation Fault masking5 N+1 redundancy Dynamic or persistent deallocationServiceability Error indication and LED indicatorsManageability Concurrent MaintenanceAdvanced System Management Interface Service Agent Advanced System Management main menuService focal point Service Update Management Assistant3 p5 Customer-Managed Microcode Cluster CSM value points CSM V1.4 on AIX and Linux planned 4Q04IBM Redbooks Other publicationsOnline resources How to get IBM Redbooks Help from IBM68 p5-570 Technical Overview and Introduction Page IBM Eserver p5 Technical Overview Introduction

P5 570 specifications

The IBM P5 570 is a high-performance server that was designed for enterprise-scale computing, offering a blend of advanced technologies and a flexible architecture. Launched as part of IBM's Power5 server line, the P5 570 stands out for its robust processing capabilities and extensive scalability, making it a preferred choice for businesses requiring reliable and efficient computing solutions.

At the heart of the P5 570 is the IBM Power5 processor, which employs simultaneous multi-threading (SMT) technology. This allows the processor to handle two threads per core, effectively doubling the throughput for workloads ideally suited to multi-threading. The server typically features a configuration of up to 32 Power5 processors, providing an impressive compute power that supports demanding applications, ranging from databases to complex enterprise resource planning (ERP) systems.

The P5 570 architecture supports a wide range of memory configurations, with a maximum memory capacity of up to 512 GB. Utilizing IBM’s proprietary Chip Memory technology, it can deliver high bandwidth and low latency, significantly enhancing performance for memory-intensive applications. Furthermore, the integrated memory controller architecture optimizes memory access, ensuring that critical workloads run smoothly.

Scalability is a key characteristic of the P5 570, with the ability to expand processing power and memory capacity as an organization’s needs grow. The server supports various operating systems, including AIX, Linux, and IBM i, which provides flexibility for diverse IT environments. This versatility ensures that companies can run their preferred applications without the need for substantial system overhauls.

In terms of storage, the P5 570 utilizes advanced RAID technology and supports a variety of disk configurations, ensuring that data integrity and availability are maintained. Coupled with built-in security features, such as the IBM Trusted Foundation, which establishes a secure boot environment, the P5 570 offers a reliable platform for mission-critical workloads.

Finally, the IBM P5 570 is designed for high availability and redundancy. Features like hot-swappable components and advanced error detection and recovery mechanisms minimize downtime, making it a dependable choice for businesses that operate around the clock. Combined with its powerful hardware and versatile software support, the IBM P5 570 remains a formidable player in the high-performance server arena.
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