Advanced Availability Functions
Transparent Sparing
z890 offers a 5 PU MCM in the case of processor failure. If there is a spare PU available it will be used for transparent sparing. Note this can only be achieved on
Enhanced Dynamic Memory Sparing
The z890 has enhanced this robust recovery design with 16 times more chips available for sparing. This will virtually eliminate the need to replace a memory card due to DRAM failure.
Enhanced Storage Protect Keys: z890 has enhanced the memory storage protect key design by adding a third key array to each memory card. The arrays are parity checked and employ a Triple Voting strategy to assure accuracy.
This will reduce the need for memory card replacement due to key array failure.
ESCON Port Sparing: The ESCON
Concurrent Maintenance
•Concurrent Service for I/O Cards: All the cards which plug into the new I/O Cage are able to be added and replaced concurrent with system operation. This virtually eliminates any need to schedule outage to service or upgrade the I/O subsystem on this cage.
•Upgrade for Coupling Links: z890 has concurrent main- tenance for the
•Cryptographic Cards: The PCIXCC and PCICA cards plug in the I/O cage and can be added or replaced concurrently with system operation.
•Redundant Cage Controllers: The Power and Service Control Network features redundant Cage Controllers for Logic and Power control. This design enables nondis- ruptive service to the controllers and virtually eliminates customer scheduled outage.
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Concurrent Capacity BackUp Downgrade (CBU Undo)
This function allows the customer to downgrade the disas- ter backup machine to its normal confi guration without requiring the PowerOn Reset (POR).
Fault Tolerant Interconnect Design: The memory design of the z890 provides a fault tolerant dual interconnect fabric. The z890 is designed to prevent a single failure within the fabric from disrupting full memory access.
Concurrent Capacity Upgrade: A z890 can be upgraded via the concurrent addition of additional Processor Units (PUs) and I/O and limited memory upgrades (24 Gb to 32 Gb increment) with no disruption to current operations. However, while capacity upgrades to the processor itself are concurrent, your software may not be able to take advantage of the increased capacity without performing an Initial Programming Load (IPL).
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