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| FUNCTIONAL | DESCRIPTION | |||
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| F . LINE | STATUS | REGISTER |
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D7 | FFRX | Error | in FIFO RCVR | (FIFO only) | ||||
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D6 | TEMT | Transmitter | empty |
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D5 | THRE | Transmitter | holding | register empty | ||||
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D4 | BI | Break | interrupt |
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D3 | FE | Framing | error |
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D2 | PE | Parity | error |
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D1 | OE | Overrun | error |
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| + |
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D0 | DR | Data ready |
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| + |
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Figure 12. Line status register bit definitions.
FFRX - | FIFO Receiver Error: | |||
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| Always logic 0 in character mode. | ||
FIFO | mode: |
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| I n d i c a t e s o n e o r m o r e p a r i t y e r r o r s , f r a m i n g | ||
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| e r r o r s , o r b r e a k i n d i c a t i o n s i n t h e r e c e i v e r | ||
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| FIFO. FFRX is reset by reading the line status | ||
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| register. |
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TEMT | - | Transmitter | Empty: | |
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| Indicates | the transmitter holding register (or | |
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| F I F O ) a n d t h e t r a n s m i t t e r s h i f t r e g i s t e r a r e | ||
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| empty and are ready to receive new data. TEMT is | ||
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| reset by writing a character to the transmitter | ||
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| holding | register. | |
THRE - | Transmitter Holding Register Empty: | |||
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| Indicates | the transmitter holding register (or | |
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| F I F O ) i s e m p t y a n d i t i s r e a d y t o a c c e p t n e w | ||
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| d a t a . | T H R E i s r e s e t b y w r i t i n g d a t a t o t h e | |
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| transmitter | holding register (or FIFO). | |
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