IBM DS-2000 warranty OUT PUT Configurations IX. Output Configurations

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OUT

PUT CONFIGURATIONS

IX. OUTPUT CONFIGURATIONS

Two sets of jumpers are implemented on the DS-2000 to control the auxiliary driver/receiver set. Jumpers J2 and J3 perform identical functions on channels 1 and 2 respectively.

The function of J2 and J3 is to control the source o f t h e d a t a e x c h a n g e d o n t h e a u x i l i a r y c o m m u n i c a t i o n lines . The output sources are request to send (RTS), transmit clock (XCLK), and the auxiliary input (AUX IN). T h e i n p u t s a r e c l e a r t o s e n d ( C T S ) a n d r e c e i v e c l o c k (RCLK).

Transmission of RTS, when combined with reception of clear to send (CTS), allows for handshaking between the 16550 and a peripheral device . RTS is transmitted by connecting pins 5 and 6 of the jumper block (figure 21). CTS is received by connecting pins 1 and 2 (figure 21). The RTS/CTS handshake can be defeated by looping the RTS output back to the CTS input. This is accomplished by connecting pins 1 and 5 of the jumper block (figures 22 and 23).

RCLK is the input to the 16550 which controls the s h i f t r a t e f o r t h e r e c e i v e r p o r t i o n o f t h e c h i p . Generally this input is provided by connecting it to the XCLK output. This is performed by connecting pins 3 and

7

of the jumper block (figures 21 and 23). RCLK may be

received

from an external source by connecting pins 2 and

3

(figure

22).

Transmission of XCLK can be used to help synchronize communications with a peripheral or to provide a shift c l o c k f o r a r e c e i v e r . T r a n s m i s s i o n o f X C L K i s accomplished by connecting pins 6 and 7 of the jumper block (figure 22).

AUX IN is the auxiliary input from a peripheral device. Connecting AUX IN to AUX OUT provides a loopback mode of operation. That is, whatever is transmitted by the peripheral will be fed back to the peripheral. AUX IN/ AUX OUT loopback is implemented by connecting pins 2 and 6 of the jumper (figure 23).

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Contents Date of Purchase Warranty InformationSerial Number Table of Contents Fifo ListModem CPU IntroductionII . Board Description Functional Description Functional Description III Functional Dlab Register DescriptionFunctional Description Interrupt Enable Register Functional Description Interrupt Identification Register Func Tional Description IID2 IID1 IID0 IPFunctional Description Fifo Control Register Line Control Register Parity selections STB STB WLS1 WLS0Functional Description Modem Control Register Temt Functional Description Line Status RegisterFfrx ThreData ready Indicates Is present Receive buffer Functional Description Modem Status Register Baud Rate Selection Fifo Interrupt Mode OperationFunctional Description Scratchpad Register PC/XTAUD Rate Selection VII Interrupts Addressing VI. AddressingVIII. Programmable Option Select Programm Able Option Select Programmable Option Select Available interrupt levels IiiOUT PUT Configurations IX. Output Configurations Output Configurations Auxin Rclk Rclk AuxinBaudout Auxout DTR RTSOutput Configurations Ternal Connections External Connections Installation XI. Installation XII Specifications