FUNCTIONAL DESCRIPTION
H . SCRATCHPAD REGISTER
This register is not used by the 16550. It may be used by the programmer for data storage.
IV. | FIFO INTERRUPT MODE OPERATION | |
1. The | receive data interrupt is | issued when the FIFO |
r e a c h e s t h e t r i g g e r l e v e l . | T h e i n t e r r u p t i s | |
cleared as soon as the FIFO falls below the trigger level.
2.The interrupt identification register's receive data available indicator is set and cleared along with the receive data interrupt above.
3 . T h e d a t a r e a d y i n d i c a t o r i s s e t a s s o o n a s a character is transferred into the receiver FIFO and is cleared when the FIFO is empty.
V. BAUD RATE SELECTION
T h e 1 6 5 5 0 U A R T d e t e r m i n e s t h e b a u d | r a t e o f t h e |
s e r i a l o u t p u t f r o m a c o m b i n a t i o n o f t h e | c l o c k i n p u t |
frequency and the value written to the divisor latches.
Standard | PC, | PC/XT, | PC/AT, and | PS/2 | serial interfaces use |
an input | clock of | 1.8432 MHz. | To | increase versatility, | |
t h e D S - 2 0 0 0 | u s e s a n 1 8 . 4 3 2 M H z c l o c k a n d a f r e q u e n c y | ||||
divider circuit to produce the standard clock frequency. | |||||
Jumper block J1 is used to set the frequency of the | |||||
16550. | It may be | connected to | divide the clock input by | ||
1 , 2 , 5 , o r 1 0 . | F o r c o m p a t i b i l i t y , J 1 s h o u l d b e | ||||
c o n f i g u r e d t o d i v i d e b y 1 0 a s s h o w n i n f i g u r e 1 4 ( d ) .
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