ADDRESSING
VI. ADDRESSING
Each channel of the
but | must | begin on | an even |
or | xxx8H | - xxxFH). | The numbers xxx are controlled by the |
Programmable Option Select (POS) and address decoders to p r o v i d e c o m p l e t e 1 6 - b i t a d d r e s s i n g f o r e a c h c h a n n e l . Sixteen choices of base address are provided for each
channel and include | the eight addresses defined as SERIAL |
1 through SERIAL 8. | The remaining eight addresses are a |
c o n s t a n t 8 0 0 0 H o f f s e t f r o m t h e s e v a l u e s . A c o m p l e t e table of available addresses is given in figure 17. The 16550 utilizes its eight assigned addresses as shown in figure 2.
VII. | INTERRUPTS |
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The | capable | of | supporting | four | interrupt | |
l e v e l s , I R Q 3 , 4 , 7 a n d 9 . | E a c h c h a n n e l m a y s e l e c t a | |||||
separate interrupt or | one may | be | shared by | both | channels. | |
If interrupt sharing is used, the interrupt pending (IP) bit in the interrupt identification register should be used to test for the source of the interrupt.
CAUTION:
T o m a i n t a i n c o m p a t i b i l i t y w i t h e a r l i e r p e r s o n a l computer systems, the user defined output, OUT 2, is used as an external interrupt enable and must be set active for interrupts to be acknowledged. OUT 2 is accessed through the 16550's MODEM control register.
VIII. PROGRAMMABLE OPTION SELECT
T h e I B M P S / 2 f a m i l y o f c o m p u t e r s u s i n g t h e MicroChannel bus structure utilize on board registers r e f e r r e d t o a s t h e P r o g r a m m a b l e O p t i o n S e l e c t ( P O S ) r e g i s t e r s t o h o l d t h e a d a p t e r ' s c o n f i g u r a t i o n information. The first two POS registers hold a unique adapter identification number that has been issued to Qua Tech for the
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